System Design Guidelines for LM3S Stellaris ...

1 ApplicationReportSPMA036B September2011 RevisedFebruary2013 SystemDesignGuidelinesforStellaris MicrocontrollersABSTRACTS tellaris LM3 SandLM4 Fmicrocontrollersarehighly-integratedsys tem-on-chip(SOC) ,therearemanyfactorstoconsiderwhencreati nga schematicanddesigninga ,youwillincreaseyourconfidencethattheboa rdwillworkthefirsttimeit is poweredit MicrostripDifferentialPairona Four-Layer, MicrostripDifferentialPairona Four-Layer, , a September2011 RevisedFebruary2013 SystemDesignGuidelinesforStellaris MicrocontrollersSubmitDocumentationFeedb ackCopyright 2011 2013, (Section3). Topicsincludeimportantfactorsin theschematicdesignandlayoutofpowersuppli es,oscillators, ,allowingyoutoselecttheinformationthatis relevanttoyourdesign(Section4).Tofurther assistyouwiththedesignprocess,TexasInstr umentsprovidesa widerangeofadditionaldesignresources, (Section6) thisdesignguideis intendedtobegeneralenoughtocovera ,becauseeverysystemis different,it is especiallytruein designsthatincludehigh-performanceanalog circuits,radiofrequencies,highvoltages, yourdesignincludesthesefeatures,thenspec ialconsiderations(beyondthescopeofthisap plicationreport) ,thedistinctionis madebetweenpreferredpracticeandacceptabl epractice.

2 Thisdistinctionaddressestherealitythatco nstraintssuchassize,cost, Design ,oneofthemostimportantfactorsis thereis onlylow-speed,low-currentswitchingontheS tellarisperipheralpins, high-speedswitchingis present,particularlywithsimultaneoustran sitions(forexample,theEPImodule), :Someoftheinformationin : Power Reset Oscillators JTAGI nterface System AllExternalSignals2 SystemDesignGuidelinesforStellaris MicrocontrollersSPMA036B September2011 RevisedFebruary2013 SubmitDocumentationFeedbackCopyright 2011 2013, , single+ ,lowdrop-out(LDO) thecorevoltage(VDDCorVDD25) becauseit ;seethePowerControlsectionoftheSystemCon trolchapterin therespectivedatasheettodetermineif a ,a designermightwishtousea switchingpowersupplytoreducepowerlossin typicalswitchingregulatorhasanefficiency of85%comparedto36%fora VDDC switchingsupplyis touseVDD(+ ) , anexternalVDDC sourceis used,theon-chipLDOregulatormuststillhave a ,LDOF ilterCapacitor, smallreductionin ,thepower-supplyrailmustremainwithinthee lectricallimitslistedin themicrocontrollerdatasheet[VDD(min)andV DD(max)].

3 Foroptimalperformanceoftheon-chipanalogm odules, ,relays,andotherpower-switchingcircuitss houldeachhavea separatesupplyrail,especiallyif analog-to-digitalconverter(ADC)performan ceis a (POR)circuitreleasesoncetheVDDpower-supp lyrailreachesthePORthresholdVth. Thebrown-outreset(BOR)circuitis a moreprecisesupplyrailmonitorandisnormall yusedtoholdthemicrocontrollerin resetif ,thedefaultBORactionis togeneratea ,onotherStellarisdevices,thesoftwaremust configuretheBORtogeneratea ,brown-out, September2011 RevisedFebruary2013 SystemDesignGuidelinesforStellaris MicrocontrollersSubmitDocumentationFeedb ackCopyright 2011 2013, , , filtercapacitortooperateproperly(seetheC LDO parameterin thecorrespondingmicrocontrollerdatasheet foracceptablecapacitorvalues).TheLDOcapa citanceis ,theLDOpincapacitoris 1 F F F F,10V to25V,X5R/X7 Rwith20% F F (thatis, F Fcapacitors). anexternalVDDC sourceis used,theon-chipLDOregulatormustcontinuet ohavea , ,Stellarismicrocontrollersshouldhaveoned ecouplingcapacitorin F F in valueandshouldbeaccompaniedbya typicallybetween2 F and22 F,withvaluesontheupperendofthatrangeprov idingmeasurableripplereductionin someapplications,especiallyif particularlyimportantif themicrocontrolleris connectedtohigh-speedinterfacesorneedsto sourcesignificantGPIO current(thatis,greaterthan4 mA) , minimum, to25V,X5 [(Cain,Jeffrey,ComparisonofMultilayerCer amicandTantalumCapacitors,AVXT echnicalBulletin.)]

4 ] , MicrocontrollersSPMA036B September2011 RevisedFebruary2013 SubmitDocumentationFeedbackCopyright 2011 2013,TexasInstrumentsIncorporatedCapCapC apVDDGNDCapVDDGNDCapVDDGNDCapVDDGNDBest practiceMinimal inductance frombetween capacitor, pins andpower recommendedDistance from pins to viasincreases inductance inpower to VDD andGND planes is GND trace fromthe pin to capacitor is notoptimal, the inductance frompins to power places is recommendedVia is located too far fromGND pin, adding inductanceto the locations are as close topins as possible. Traces tocapacitor are as short showdifferentoptionsforroutingPCBtracesb etweentheStellarismicrocontrollerpowerpi nsanda September2011 RevisedFebruary2013 SystemDesignGuidelinesforStellaris MicrocontrollersSubmitDocumentationFeedb ackCopyright 2011 2013, , , VDDA, GND,andMicrocontrollerdatasheetrecommend ationsmicrocontrollersGNDA pinsStellarismicrocontrollersaredesigned tooperatewithVDDandVDDA pinsconnecteddirectlytothesame+ , ,VDDA canbeselectedasa ,the12-bitADCachievesoptimalperformancew henpoweredwitha conjunctionwitheithera low-valueresistororinductor/ferritebeadt oforma theVDDandVDDA pinsaresplit,thedesignermustensurethatpo weris preferablytoa , specialexternalresetcircuitis (POR)circuitwitha + ,a resistor(1k ) to+ andacapacitor( F) ,it is particularlyimportantin ( ) theRSTsignalsourceis anotherboard,it is recommendedtoadda simplepush-switchcanbeusedtoprovidea ,adda low-valueresistor(100 )

5 In MicrocontrollersSPMA036B September2011 RevisedFebruary2013 SubmitDocumentationFeedbackCopyright 2011 2013,TexasInstrumentsIncorporatedOSC0LM4 FMicrocontrollerC1C2 RSCrystalOSC1(a)Main Oscillator CircuitLM4F DevicesLM3 SMicrocontrollerOSC0 CSC1C2 CSCrystalOSC1(b)Main Oscillator CircuitLM3S DevicesLM4 FMicrocontrollerXOSC0C1C2 CrystalXOSC1 GNDX(c)Hibernate ModuleOscillator CircuitLM4F , mainoscillatorcircuittoprovidea ,parallel-resonantoscillatorcircuitrequi resanexternalcrystal(seeFigure2) andtwoloadcapacitorstocompletethecircuit (thelow-powerHibernationmoduleoscillator onsomedevicesmayalsorequirea 1-M seriesresistor seetherespectivemicrocontrollerdatasheet fordetails). loadcapacitance(CL) whichshouldbeusedin (C1* C2) / (C1+ C2) + CSCSis thestraycapacitancein a functionoftracelengths,PCBconstruction, typicaldesign,CSshouldbeapproximately2 ,thecalculationfora typicalcircuitsimplifiesslightlyto:C1and C2= (CL 3 pF)* 2 Forexample,theDK-LM3S9B96 DevelopmentKitusesa 16-MHzNX5032 GAcrystalfromNDKwitha CLof8 , ,it is seriesresistor(RS) September2011 RevisedFebruary2013 SystemDesignGuidelinesforStellaris MicrocontrollersSubmitDocumentationFeedb ackCopyright 2011 2013, , pooroscillatorlayoutcanresultin unreliableorinaccurateoscillatoroperatio nandcanalsobea or6 showsa preferredlayoutfora viathatprovidesa seriesresistor(toadjustdrive)ora resistorin ,theresistorshouldbea , boardthatusesa Stellarismicrocontroller,it is , (SWCLKandSWDIO)

6 ,insteadofthefoursignalsthatJTAG requires, MicrocontrollersSPMA036B September2011 RevisedFebruary2013 SubmitDocumentationFeedbackCopyright 2011 2013, debugconnectoris a 2x10-way, is robust, ,whichis nowquitepopular,usesa , ,6,8,10,12,14,16,18,203,5,9 TVCC11 SomeStellarismicrocontrollershavea ofthe20-pinARMconnector,butis notnormallyconnectedbecausea Testresetis weakinternalpull-uponTCK,TDI,TMS,TDO,and TRST(ifapplicable)outofreset, ,ata minimum,TCK,TMS,andTRST(wherepresent)sho uldhavepull-upresistorsto+ toprovidea safestatewhenadebugcableis , tablein theSignalschapterthatliststhefixedfuncti onpinsaswellasboththeacceptablepracticea ndthepreferredpracticeforreducedpowercon sumptionandimprovedelectromagneticcompat ibility(EMC) a moduleis notusedin a System ,anditsinputsaregrounded,it is importantthattheclocktothemoduleis September2011 RevisedFebruary2013 SystemDesignGuidelinesforStellaris MicrocontrollersSubmitDocumentationFeedb ackCopyright 2011 2013,TexasInstrumentsIncorporated90 Acceptable PCBtrace routingAlso acceptablePCB trace :90 , Microcontrollerdatasheetonhigh-speednets recommendationsmicrocontrollers ReferencedesignPCBfilesFormanyyears,it hasbeencommonPCBdesignpracticetoavoid90 cornersin ,mostPCBlayouttoolshavea built-inmitercapabilitytoautomaticallyre place90 angleswithtwo45 thatthesignal-integritybenefitsofavoidin g90 anglesareinsignificantatthefrequenciesan dedge-ratesseenin microcontrollercircuits(evenuptoandpast1 GHz/100ps).

7 [Johnson,H andGraham,M,High-SpeedDigitalDesign:a HandbookofBlackMagic, PrenticeHall:NewJersey,1993.]Additionall y,onereportcouldfindnomeasurabledifferen cein radiatedelectromagneticinterference(EMI) .[Montrose,MarkI, RightAngleCornersonPrintedCircuitBoardTr aces,TimeandFrequencyDomainAnalysis, undated.] :Loopsin PCBtracesarenotacceptable,despitetherefe rencesthatindicatethatthesignal-integrit ybenefitsofavoiding90anglesis yourlayoutdoeshaveantennaloops,thenmiter ingtheanglesto135 is ,therearea fewsimplereasonstocontinuetoavoid90 angles: Thereis a higherpossibilityofanacid-trapformingdur ingetchingontheinsideoftheangle(especial lyin acuteangles).Anacidtrapcausesover-etchin gwhichcanbea yieldissuein PCBswithsmalltracewidths. Routingat45 ,reducescurrentloops,andimprovesbothEMCe missionsandimmunity. It MicrocontrollersSPMA036B September2011 RevisedFebruary2013 SubmitDocumentationFeedbackCopyright 2011 2013, groupedbyfunctionorperipheral: EthernetMACandPHY EthernetandUSB USB EPI GeneralGuidelinesforAllHigh-SpeedInterfa ces , MicrocontrollerdatasheetwithEthernetMACa ndbiasresistorsrecommendations EvaluationboardschematicsPHYA ,TXON,RXIP,andRXIN signalsto+ 50.

8 Therecommended,commonlyavailablevalueis , 1%.Donotuseresistorswithatolerancegreate rthan1%.Resistorpowerdissipationis lowbecausethepeakvoltageontheresistoriso nlyapproximately1 ,0402(1005metric) a , MicrocontrollerdatasheetLayoutwithEthern etMACandcomponents EvaluationboardschematicsPHYTheStellaris datasheetslistboththepartnumberandmanufa cturer'snameforseveralapprovedEthernettr ansformer(magnetics) ,butit is connectorwithintegratedtransformerora namedTXOP/ in fact, (microcontroller-sideofthetransformer)sh ouldbeconnectedto+ + capacitor( F orgreater)ifa solidpower-planeis ,orif thecentertapconnectstoa PCBtrace,thecapacitorvalueshouldbe1 F September2011 RevisedFebruary2013 SystemDesignGuidelinesforStellaris MicrocontrollersSubmitDocumentationFeedb ackCopyright 2011 2013,TexasInstrumentsIncorporated1-oz Copper (Signal Layer)1-oz Copper (Power Plane)1-oz Copper (Ground Plane)1-oz Copper (Signal Layer)2 Sheets 2116 ( ")2 Sheets 2116 ( ")

9 " " +/- 10% , MicrocontrollerdatasheetAllStellarisPCBl ayoutguidelinesfortheStellarisSchematicm icrocontrollerswith ReferencedesignPCBfilesoscillatorcircuit srecommendationsEthernetMACandPHY 100- differentialimpedanceis a , performedbythePCBfabhouse, preferred,it maybeacceptabletoskipthatstepif thetracelengthis lessthanapproximately2 in ( ).If gooddesignrulesarefollowedduringlayout,i t ,theStellarislabhascompletedsixdesignswi ththisapproach, slightvariationofthismethod,whichalsoavo idstheadditionalcostofcontrolled-impedan cePCBs,issometimescalledcontrolleddielec tric. ThisapproachinvolvesthePCBdesignerusinga dielectricspecificationthatis ImpedanceSomePCBdesigntoolshaveanintegra tedtraceimpedancecalculatorthatfactorsin tracegeometry,tracelength,boardstack-up, ,ensurethatthedifferentialimpedance(impe dancebetweenthesignalsin thepair)is 100 . If a groundplaneis present,thesingle-endedimpedance(ZO) shouldbe50 .Thetypicaldielectricconstant(ER) forFR-4materialis typicalconfigurationforanFR-4, ( )circuitboardwithfourlayersof1-ozcopper( noplating)is shownin MicrocontrollersSPMA036B September2011 RevisedFebruary2013 SubmitDocumentationFeedbackCopyright 2011 2013,TexasInstrumentsIncorporated1-oz Copper (Signal Layer)1-oz Copper (Power Plane)1-oz Copper (Ground Plane)1-oz Copper (Signal Layer)2 Sheets 2116 ( ")2 Sheets 2116 ( ") " Core+ " " "+Er-+ ,weplacea (.)

10 0014in, ) definedbythethicknessofthePCBprepregmate rial in thiscase, ( ) ,totalthicknessis:Totalthickness= = 4 x + + 2 x impedance, PCBwitha conductorboundedbya singlegroundreferenceplaneis knownasa microstrip,asshownin moreadvancedconfiguration,knownasstripli ne,usestwoground-referenceplaneswhichare typicallystitchedtogetherwithviastoforma ,Inc.,resultsin thefollowingvaluesfortheboardstackshowni n (W)= ( )Conductorspacing(S)= ( )Substratethickness(H)= ( )ZDifferential= ZO= 54 HyperLynxfromMentorgraphicsgivesthefollo wingsimilarresults:Conductorwidth(W)= ( )Conductorspacing(S)= ( )Substratethickness(H)= ( )ZDifferential= ZO= TheHyperLynxmodelis morecompletebecauseit alsofactorsin MicrostripDifferentialPairona Four-Layer, September2011 RevisedFebruary2013 SystemDesignGuidelinesforStellaris MicrocontrollersSubmitDocumentationFeedb ackCopyright 2011 2013, two-layerboard,theheightofthesubstrateis difficulttoachieveanythingcloseto50- single-endedimpedance(ZO).