TDA8932B Class-D audio amplifier

1 1. General descriptionThe TDA8932B is a high efficiency Class-D amplifier with low power continuous time output power is 2 15 W in stereo half-bridge application (RL=4 )or 1 30 W in mono full-bridge application (RL=8 ). Due to the low power dissipationthe device can be used without any external heat sink when playing music. Due to theimplementation of thermal foldback, even for high supply voltages and/or lower loadimpedances, the device continues to operate with considerable music output powerwithout the need for an external heat device has two full-differential inputs driving two independent outputs. It can be usedin a mono full-bridge configuration (BTL) or in a stereo half-bridge configuration (SE).

2 2. FeaturesnOperating voltage from 10 V to 36 V asymmetrical or 5 V to 18 V symmetricalnMono-bridged tied load (full-bridge) or stereo single-ended (half-bridge) applicationnApplication without heat sink using thermally enhanced small outline packagenHigh efficiency and low-power dissipationnThermally protected and thermal foldbacknCurrent limiting to avoid audio holesnFull short-circuit proof across load and to supply lines (using advanced currentprotection)nSwitchable internal or external oscillator (master-slave setting)nNo pop noisenFull-differential inputs3. ApplicationsnFlat panel television setsnFlat panel monitor setsnMultimedia systemsnWireless speakersnMini and micro systemsnHome sound setsTDA8932 BClass-D audio amplifierRev.

3 04 18 December 2008 Product data sheetTDA8932B_4 NXP 2008. All rights data sheetRev. 04 18 December 20082 of 48 NXP SemiconductorsTDA8932 BClass-D audio amplifier4. Quick reference data[1]Output power is measured indirectly; based on RDSon measurement.[2]Two layer application board (55 mm 45 mm), 35 m copper, FR4 base material in free air with Ordering informationTable reference dataVP= 22 V; fosc= 320 kHz; Tamb =25 C; unless otherwise voltageasymmetrical supply102236 VIPsupply currentSleep mode-145195 AIq(tot)total quiescentcurrentOperating mode; no load, nosnubbers and no filterconnected- 4050mAStereo SE channel; Rs< [1]Po(RMS)RMS output powercontinuous time output powerper channel;THD+N = 10 %; fi= 1 kHzRL=4 ; VP= 22 ; VP= 30 time output power perchannel; THD+N = 10 %;fi= 1 kHz[2]RL=4 ; VP= 29 BTL; Rs< [1]Po(RMS)RMS output powercontinuous time output power;THD+N = 10 %; fi= 1 kHzRL=4 ; VP= 12.

4 VP= 22 time output power;THD+N = 10 %; fi= 1 kHz[2]RL=8 ; VP= 29 informationType numberPackageNameDescriptionVersionTDA89 32 BTSO32plastic small outline package; 32 leads;body width mmSOT287-1 TDA8932 BTW HTSSOP32 plastic thermal enhanced thin shrink small outlinepackage; 32 leads; body width mm; lead mm; exposed die padSOT549-1 TDA8932B_4 NXP 2008. All rights data sheetRev. 04 18 December 20083 of 48 NXP SemiconductorsTDA8932 BClass-D audio amplifier6. Block diagramFig diagram001aaf597210318282927312 TDA8932 BOSCILLATOR26 BOOT1 VDDP1 OUT1 VSSP1 PWMMODULATORDRIVERHIGHDRIVERLOWCTRLMANAG ERCTRLPWMMODULATORPROTECTIONS:OVP, OCP, OTP,UVP, TF, WPSTABILIZER 11 VSTABILIZER 11 VREGULATOR 5 VMODEVDDA1514IN1 POSCREFOSCIOVDDAVSSDIN1 NINREFIN2 PIN2N6 POWERUP4 DIAG7 CGND21202223 BOOT2 VDDP2 OUT225 STAB124 STAB21811 DREFHVPREF30 HVP119 HVP2 VSSP2 DRIVERHIGHDRIVERLOWVDDAVSSP1 VSSP2 VSSDVDDAVSSAHALF SUPPLY VOLTAGE5 ENGAGE139 TESTVSSA1, 16, 17, 32 VSSD(HW)TDA8932B_4 NXP 2008.

5 All rights data sheetRev. 04 18 December 20084 of 48 NXP SemiconductorsTDA8932 BClass-D audio amplifier7. Pinning Pin descriptionFig configuration SO32 Fig configuration HTSSOP32 TDA8932 BTVSSD(HW)VSSD(HW)IN1 POSCIOIN1 NHVP1 DIAGVDDP1 ENGAGEBOOT1 POWERUPOUT1 CGNDVSSP1 VDDASTAB1 VSSASTAB2 OSCREFVSSP2 HVPREFOUT2 INREFBOOT2 TESTVDDP2IN2 NHVP2IN2 PDREFVSSD(HW)VSSD(HW)001aaf5981234567891 0111213141516181720192221242326253231302 92827 TDA8932 BTWVSSD(HW)VSSD(HW)IN1 POSCIOIN1 NHVP1 DIAGVDDP1 ENGAGEBOOT1 POWERUPOUT1 CGNDVSSP1 VDDASTAB1 VSSASTAB2 OSCREFVSSP2 HVPREFOUT2 INREFBOOT2 TESTVDDP2IN2 NHVP2IN2 PDREFVSSD(HW)VSSD(HW)001aaf5991234567891 0111213141516181720192221242326253231302 92827 Table descriptionSymbolPinDescriptionVSSD(HW)

6 1negative digital supply voltage and handle wafer connectionIN1P2positive audio input for channel 1IN1N3negative audio input for channel 1 DIAG4diagnostic output; open-drainENGAGE5engage input to switch between Mute mode and Operating modePOWERUP6power-up input to switch between Sleep mode and Mute modeCGND7control ground; reference for POWERUP, ENGAGE and DIAGVDDA8positive analog supply voltageVSSA9negative analog supply voltageOSCREF10input internal oscillator setting (only master setting)HVPREF11decoupling of internal half supply voltage referenceINREF12decoupling for input reference voltageTEST13test signal input; for testing purpose onlyIN2N14negative audio input for channel 2IN2P15positive audio input for channel 2 VSSD(HW)16negative digital supply voltage and handle wafer connectionVSSD(HW)17negative digital supply voltage and handle wafer connectionDREF18decoupling of internal (reference) 5 V regulator for logic supplyTDA8932B_4 NXP 2008.

7 All rights data sheetRev. 04 18 December 20085 of 48 NXP SemiconductorsTDA8932 BClass-D audio amplifier [1]The exposed die pad has to be connected to VSSD(HW).8. Functional GeneralThe TDA8932B is a mono full-bridge or stereo half-bridge audio power amplifier usingclass-D technology. The audio input signal is converted into a Pulse Width Modulated(PWM) signal via an analog input stage and PWM modulator. To enable the output powerDiffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWMsignal is applied to a control and handshake block and driver circuits for both the high sideand low side. A 2nd-order low-pass filter converts the PWM signal to an analog audiosignal across the TDA8932B contains two independent half-bridges with full differential input loudspeakers can be connected in the following configurations: Mono full-bridge: Bridge Tied Load (BTL) Stereo half-bridge: Single-Ended (SE)The TDA8932B contains common circuits to both channels such as the oscillator, allreference sources, the mode functionality and a digital timing manager.

8 The followingprotections are built-in: thermal foldback, temperature, current and voltage supply output voltage 2 for charging single-ended capacitor forchannel 2 VDDP220positive power supply voltage for channel 2 BOOT221bootstrap high-side driver channel 2 OUT222 PWM output channel 2 VSSP223negative power supply voltage for channel 2 STAB224decoupling of internal 11 V regulator for channel 2 driversSTAB125decoupling of internal 11 V regulator for channel 1 driversVSSP126negative power supply voltage for channel 1 OUT127 PWM output channel 1 BOOT128bootstrap high-side driver channel 1 VDDP129positive power supply voltage for channel 1 HVP130half supply output voltage 1 for charging single-ended capacitor forchannel 1 OSCIO31oscillator input in slave

9 Configuration or oscillator output in masterconfigurationVSSD(HW)32negative digital supply voltage and handle wafer connectionExposed diepad-HTSSOP32 package only[1]Table description ..continuedSymbolPinDescriptionTDA8932B_ 4 NXP 2008. All rights data sheetRev. 04 18 December 20086 of 48 NXP SemiconductorsTDA8932 BClass-D audio Mode selection and interfacingThe TDA8932B supports four operating modes, selected using pins POWERUP andENGAGE: Sleep mode: with low supply current. Mute mode: the amplifiers are switching idle (50 % duty cycle), but the audio signal atthe output is suppressed by disabling the Vl-converter input stages. The capacitors onpins HVP1 and HVP2 have been charged to half the supply voltage (asymmetricalsupply only).

10 Operating mode: the amplifiers are fully operational with output signal. Fault POWERUP and ENGAGE are referenced to pin shows the different modes as a function of the voltages on the POWERUP andENGAGE pins.[1]In case of symmetrical supply conditions the voltage applied to pins POWERUP and ENGAGE must neverexceed the supply voltage (VDDA, VDDP1 or VDDP2).If the transition between Mute mode and Operating mode is controlled via a time constant,the start-up will be pop free since the DC output offset voltage is applied gradually to theoutput between Mute mode and Operating mode. The bias current setting of theVI-converters is related to the voltage on pin ENGAGE: Mute mode: the bias current setting of the VI-converters is zero (VI-convertersdisabled) Operating mode: the bias current is at maximumThe time constant required to apply the DC output offset voltage gradually between Mutemode and Operating mode can be generated by connecting a 470 nF decouplingcapacitor to pin selectionModePinPOWERUPENGAGEDIAGS leep< V< Vdon t careMute2 V to V[1]< V[1]> 2 VOperating2 V to V[1] V to V[1]>2 VFault2 V to V[1]don t care< VTDA8932B_4 NXP 2008.