Transcription of TMS320x2833x, 2823x DSC Serial Peripheral Interface (SPI
1 TMS320x2833x, 2823xSerialPeripheralInterf ace(SPI)ReferenceGuideLiteratureNumber:S PRUEU3 AAugust2008 RevisedJune20092 SPRUEU3A August2008 (SPI).. (SPICCR).. (SPICTL).. (SPIST).. (SPIBRR).. (SPIRXEMU).. (SPIRXBUF).. (SPITXBUF).. (SPIDAT).. ,Receive, (SPIPRI).. August2008 :SPICLK-CLKOUTC haracteristicWhen(BRR+1)isOdd,BRR>3,andC LOCKPOLARITY= (SPICCR) (SPICTL) (SPIST) (SPIBRR) (SPIRXEMU) (SPIRXBUF) (SPITXBUF) (SPIDAT) (SPIFFTX)Register (SPIFFRX)Register (SPIFFCT)Register ,CLOCKPHASE=0(Alldatatransitionsaredurin gtherisingedge, )..352-13 CLOCKPOLARITY=0,CLOCKPHASE=1(Alldatatran sitionsareduringtherisingedge, ).
2 362-14 CLOCKPOLARITY=1,CLOCKPHASE=0( )..362-15 CLOCKPOLARITY=1,CLOCKPHASE=1(Alldatatran sitionsareduringthefallingedge, )..372-16 SPISTEB ehaviorinMasterMode(MasterlowersSPISTE duringtheentire16bitsoftransmission.)..3 72-17 SPISTEB ehaviorinSlaveMode(Slave sSPISTE isloweredduringtheentire16bitsoftransmis sion.)..38 ListofFigures4 SPRUEU3A August2008 (SPICCR) (SPICTL) (SPIST) (SPIRXEMU) (SPIRXBUF) (SPITXBUF) (SPIDAT) (SPIFFTX) (SPIFFRX) (SPIFFCT) (SPIPRI) August2008 RevisedJune2009 ListofTables5 SubmitDocumentationFeedbackListofTables6 SPRUEU3A August2008 RevisedJune2009 SubmitDocumentationFeedbackPrefaceSPRUEU 3A August2008 ,28xxxDSPP eripheralReferenceGuide(SPRU566)
3 ForalistofalldeviceswithanSPImoduleofthe sametype,todeterminethedifferencesbetwee ntypes, , SPRS439 TMS320F28335,TMS320F28334,TMS320F28332,T MS320F28235,TMS320F28234,TMS320F28232 DigitalSignalControllers(DSCs)DataManual containsthepinout,signaldescriptions,asw ellaselectricalandtimingspecificationsfo rtheF2833 TMS320F28335,F28334,F28332,TMS320F28235, F28234,F28232 DigitalSignalControllers(DSCs) 'sGuides SPRU430 TMS320C28xCPUandInstructionSetReferenceG uidedescribesthecentralprocessingunit(CP U)andtheassemblylanguageinstructionsofth eTMS320C28xfixed-pointdigitalsignalproce ssors(DSPs).
4 SPRU566 TMS320x28xx,28xxxDSPP eripheralReferenceGuidedescribestheperip heralreferenceguidesofthe28xdigitalsigna lprocessors(DSPs).SPRUFB0 TMS320x2833x, 2823xSystemControlandInterr uptsReferenceGuidedescribesthevariousint erruptsandsystemcontrolfeaturesofthe2833 xand2823xdigitalsignalcontrollers(DSCs). SPRU812 TMS320x2833x, 2823xAnalog-to-DigitalConve rter(ADC)ReferenceGuidedescribeshowtocon figureandusetheon-chipADCmodule, TMS320x2833x, 2823xDSCE xternalInterface(XINTF)ReferenceGuidedes cribestheXINTF,whichisanonmultiplexedasy nchronousbus, TMS320x2833x, 2823xBootROMR eferenceGuidedescribesthepurposeandfeatu resofthebootloader(factory-programmedboo t-loadingsoftware) TMS320x2833x, 2823xMultichannelBufferedSe rialPort(McBSP) August2008 TMS320x2833x, 2823xDirectMemoryAccess(DMA ) TMS320x2833x, 2823xEnhancedPulseWidthModu lator(ePWM)
5 ModuleReferenceGuidedescribesthemainarea softheenhancedpulsewidthmodulatorthatinc ludedigitalmotorcontrol,switchmodepowers upplycontrol,UPS(uninterruptiblepowersup plies), TMS320x2833x, 2823xHigh-ResolutionPulseWi dthModulator(HRPWM)ReferenceGuidedescrib estheoperationofthehigh-resolutionextens iontothepulsewidthmodulator(HRPWM).SPRUF G4 TMS320x2833x, 2823xEnhancedCapture(eCAP) TMS320x2833x, 2823xEnhancedQuadratureEnco derPulse(eQEP)ModuleReferenceGuidedescri bestheeQEPmodule,whichisusedforinterfaci ngwithalinearorrotaryincrementalencodert ogetposition,direction, TMS320x2833x, 2823xEnhancedControllerArea Network(eCAN) TMS320x2833x, 2823xSerialCommunicationsIn terface(SCI)ReferenceGuidedescribestheSC I,whichisatwo-wireasynchronousserialport , (NRZ) TMS320x2833x, 2823xDSCS erialPeripheralInterface(SPI)ReferenceGu idedescribestheSPI-ahigh-speedsynchronou sserialinput/output(I/O)
6 Port-thatallowsaserialbitstreamofprogram medlength(onetosixteenbits) TMS320x2833x, 2823xInter-IntegratedCircui t(I2C)ModuleReferenceGuidedescribesthefe aturesandoperationoftheinter-integratedc ircuit(I2C) SPRU513 'sGuidedescribestheassemblylanguagetools (assemblerandothertoolsusedtodevelopasse mblylanguagecode),assemblerdirectives,ma cros,commonobjectfileformat, TMS320C28xOptimizingC/C++ 'sGuidedescribestheTMS320C28x C/C++ ++ TMS320C28xInstructionSetSimulatorTechnic alOverviewdescribesthesimulator,availabl ewithintheCodeComposerStudioforTMS320C20 00 IDE,thatsimulatestheinstructionsetoftheC 28x TMS320C28 (API) August2008 RevisedJune2009 SubmitDocumentationFeedbackChapter1 SPRUEU3A August2008 RevisedJune2009 SerialPeripheralInterface(SPI)Theserialp eripheralinterface(SPI)isahigh-speedsync hronousserialinput/output(I/O)
7 Portthatallowsaserialbitstreamofprogramm edlength(onetosixteenbits) ,displaydrivers,andanalog-to-digitalconv erters(ADCs). ,theportsupportsa16-level, (DSCs).ThisincludesallFlash-based, August2008 RevisedJune2009 SerialPeripheralInterface(SPI) speedprescalerSystemcontrolblockPIEblock SPIINT/RXINTTXINTR egistersSPISPIAENCLKLSPCLKSPISOMIGPIOMUX SPISIMOSPICLKSPISTEP eripheral : SPISOMI:SPIslave-output/master-inputpin SPISIMO:SPIslave-input/master-outputpin SPISTE:SPIslavetransmit-enablepin SPICLK:SPIserial-clockpinNote:Allfourpin scanbeusedasGPIO,iftheSPImoduleisnotused .
8 Twooperationalmodes:masterandslave Datawordlength:onetosixteendatabits Fourclockingschemes(controlledbyclockpol arityandclockphasebits)include: Simultaneousreceiveandtransmitoperation( transmitfunctioncanbedisabledinsoftware) (SPI)SPRUEU3A August2008 12 ,theregisterdataisinthelowerbyte(7 0),andtheupperbyte(15 8) : 16-leveltransmit/receiveFIFO DelayedtransmitcontrolSPRUEU3A August2008 RevisedJune2009 SerialPeripheralInterface(SPI) INT FLAGSPI Bit RateState ControlSPIRXBUFB uffer RegisterClockPhaseReceiverOverrun CharSPISIMOSPISOMI*SPICLKSW2 SMMSSW3To CPUMSW1 SPITXBUFB uffer RegisterRX FIFO _0RX FIFO _1 RX FIFO _15TX FIFO registersTX FIFO _0TX FIFO _1 TX FIFO _15RX FIFO registers161616TX InterruptLogicRX InterruptLogicSPIFFOVF FIFO InterruptRX FIFO / SPIRXINTSPITX / SPITXINTSPISTE , (SPI)
9 SPRUEU3A August2008 ,masteroutSPISOMISPI slaveout,masterinSPISTESPI slavetransmitenableControlSPIC lockRateLSPCLKI nterruptsignalsSPIRXINTT ransmitinterrupt/ReceiveInterruptinnonFI FO mode(referredtoasSPIINT)Receiveininterru ptinFIFO modeSPITXINTT ransmitinterrupt (x16)DescriptionSPICCR0x0000-70401 SPIC onfigurationControlRegisterSPICTL0x0000- 70411 SPIO perationControlRegisterSPIST0x0000-70421 SPIS tatusRegisterSPIBRR0x0000-70441 SPIBaudRateRegisterSPIEMU0x0000-70461 SPIE mulationBufferRegisterSPIRXBUF0x0000-704 71 SPIS erialInputBufferRegisterSPITXBUF0x0000-7 0481 SPIS erialOutputBufferRegisterSPIDAT0x0000-70 491 SPIS erialDataRegisterSPIFFTX0x0000-704A1 SPIFIFOT ransmitRegisterSPIFFRX0x0000-704B1 SPIFIFOR eceiveRegisterSPIFFCT0x0000-704C1 SPIFIFOC ontrolRegisterSPIPRI0x0000-704F1 SPIP
10 RiorityControlRegisterThisSPIhas16-bittr ansmitandreceivecapability, ,SPIDAT(andthenewtransmitbuffer,SPITXBUF ), ,alongwiththeassociatedregisters,SPIPC1( 704Dh)andSPIPC2(704Eh).Thesebitsarenowin theGeneral- : SPICCR(SPIconfigurationcontrolregister). ContainscontrolbitsusedforSPIconfigurati on SPImodulesoftwarereset SPICLK polarityselection FourSPIcharacter-lengthcontrolbitsSPRUEU 3A August2008 RevisedJune2009 SerialPeripheralInterface(SPI) SPICTL(SPIoperationcontrolregister).Cont ainscontrolbitsfordatatransmission TwoSPIinterruptenablebits SPICLK phaseselection Operationalmode(master/slave) Datatransmissionenable SPISTS(SPIstatusregister).
