TMS320x2833x, 2823x DSC Serial Peripheral Interface (SPI

1 TMS320x2833x, 2823xSerialPeripheralInterf ace(SPI)ReferenceGuideLiteratureNumber:S PRUEU3 AAugust2008 RevisedJune20092 SPRUEU3A August2008 (SPI).. (SPICCR).. (SPICTL).. (SPIST).. (SPIBRR).. (SPIRXEMU).. (SPIRXBUF).. (SPITXBUF).. (SPIDAT).. ,Receive, (SPIPRI).. August2008 :SPICLK-CLKOUTC haracteristicWhen(BRR+1)isOdd,BRR>3,andC LOCKPOLARITY= (SPICCR) (SPICTL) (SPIST) (SPIBRR) (SPIRXEMU) (SPIRXBUF) (SPITXBUF) (SPIDAT) (SPIFFTX)Register (SPIFFRX)Register (SPIFFCT)Register ,CLOCKPHASE=0(Alldatatransitionsaredurin gtherisingedge, )..352-13 CLOCKPOLARITY=0,CLOCKPHASE=1(Alldatatran sitionsareduringtherisingedge, )..362-14 CLOCKPOLARITY=1,CLOCKPHASE=0( )..362-15 CLOCKPOLARITY=1,CLOCKPHASE=1(Alldatatran sitionsareduringthefallingedge, )..372-16 SPISTEB ehaviorinMasterMode(MasterlowersSPISTE duringtheentire16bitsoftransmission.)..3 72-17 SPISTEB ehaviorinSlaveMode(Slave sSPISTE isloweredduringtheentire16bitsoftransmis sion.)

2 38 ListofFigures4 SPRUEU3A August2008 (SPICCR) (SPICTL) (SPIST) (SPIRXEMU) (SPIRXBUF) (SPITXBUF) (SPIDAT) (SPIFFTX) (SPIFFRX) (SPIFFCT) (SPIPRI) August2008 RevisedJune2009 ListofTables5 SubmitDocumentationFeedbackListofTables6 SPRUEU3A August2008 RevisedJune2009 SubmitDocumentationFeedbackPrefaceSPRUEU 3A August2008 ,28xxxDSPP eripheralReferenceGuide(SPRU566)foralist ofalldeviceswithanSPImoduleofthesametype ,todeterminethedifferencesbetweentypes, , SPRS439 TMS320F28335,TMS320F28334,TMS320F28332,T MS320F28235,TMS320F28234,TMS320F28232 DigitalSignalControllers(DSCs)DataManual containsthepinout,signaldescriptions,asw ellaselectricalandtimingspecificationsfo rtheF2833 TMS320F28335,F28334,F28332,TMS320F28235, F28234,F28232 DigitalSignalControllers(DSCs) 'sGuides SPRU430 TMS320C28xCPUandInstructionSetReferenceG uidedescribesthecentralprocessingunit(CP U)andtheassemblylanguageinstructionsofth eTMS320C28xfixed-pointdigitalsignalproce ssors(DSPs).

3 SPRU566 TMS320x28xx,28xxxDSPP eripheralReferenceGuidedescribestheperip heralreferenceguidesofthe28xdigitalsigna lprocessors(DSPs).SPRUFB0 TMS320x2833x, 2823xSystemControlandInterr uptsReferenceGuidedescribesthevariousint erruptsandsystemcontrolfeaturesofthe2833 xand2823xdigitalsignalcontrollers(DSCs). SPRU812 TMS320x2833x, 2823xAnalog-to-DigitalConve rter(ADC)ReferenceGuidedescribeshowtocon figureandusetheon-chipADCmodule, TMS320x2833x, 2823xDSCE xternalInterface(XINTF)ReferenceGuidedes cribestheXINTF,whichisanonmultiplexedasy nchronousbus, TMS320x2833x, 2823xBootROMR eferenceGuidedescribesthepurposeandfeatu resofthebootloader(factory-programmedboo t-loadingsoftware) TMS320x2833x, 2823xMultichannelBufferedSe rialPort(McBSP) August2008 TMS320x2833x, 2823xDirectMemoryAccess(DMA ) TMS320x2833x, 2823xEnhancedPulseWidthModu lator(ePWM)ModuleReferenceGuidedescribes themainareasoftheenhancedpulsewidthmodul atorthatincludedigitalmotorcontrol,switc hmodepowersupplycontrol,UPS(uninterrupti blepowersupplies), TMS320x2833x, 2823xHigh-ResolutionPulseWi dthModulator(HRPWM)ReferenceGuidedescrib estheoperationofthehigh-resolutionextens iontothepulsewidthmodulator(HRPWM).

4 SPRUFG4 TMS320x2833x, 2823xEnhancedCapture(eCAP) TMS320x2833x, 2823xEnhancedQuadratureEnco derPulse(eQEP)ModuleReferenceGuidedescri bestheeQEPmodule,whichisusedforinterfaci ngwithalinearorrotaryincrementalencodert ogetposition,direction, TMS320x2833x, 2823xEnhancedControllerArea Network(eCAN) TMS320x2833x, 2823xSerialCommunicationsIn terface(SCI)ReferenceGuidedescribestheSC I,whichisatwo-wireasynchronousserialport , (NRZ) TMS320x2833x, 2823xDSCS erialPeripheralInterface(SPI)ReferenceGu idedescribestheSPI-ahigh-speedsynchronou sserialinput/output(I/O)port-thatallowsa serialbitstreamofprogrammedlength(onetos ixteenbits) TMS320x2833x, 2823xInter-IntegratedCircui t(I2C)ModuleReferenceGuidedescribesthefe aturesandoperationoftheinter-integratedc ircuit(I2C) SPRU513 'sGuidedescribestheassemblylanguagetools (assemblerandothertoolsusedtodevelopasse mblylanguagecode),assemblerdirectives,ma cros,commonobjectfileformat, TMS320C28xOptimizingC/C++ 'sGuidedescribestheTMS320C28x C/C++ ++ TMS320C28xInstructionSetSimulatorTechnic alOverviewdescribesthesimulator,availabl ewithintheCodeComposerStudioforTMS320C20 00 IDE,thatsimulatestheinstructionsetoftheC 28x TMS320C28 (API) August2008 RevisedJune2009 SubmitDocumentationFeedbackChapter1 SPRUEU3A August2008 RevisedJune2009 SerialPeripheralInterface(SPI)Theserialp eripheralinterface(SPI)isahigh-speedsync hronousserialinput/output(I/O)portthatal lowsaserialbitstreamofprogrammedlength(o netosixteenbits) ,displaydrivers,andanalog-to-digitalconv erters(ADCs).

5 ,theportsupportsa16-level, (DSCs).ThisincludesallFlash-based, August2008 RevisedJune2009 SerialPeripheralInterface(SPI) speedprescalerSystemcontrolblockPIEblock SPIINT/RXINTTXINTR egistersSPISPIAENCLKLSPCLKSPISOMIGPIOMUX SPISIMOSPICLKSPISTEP eripheral : SPISOMI:SPIslave-output/master-inputpin SPISIMO:SPIslave-input/master-outputpin SPISTE:SPIslavetransmit-enablepin SPICLK:SPIserial-clockpinNote:Allfourpin scanbeusedasGPIO,iftheSPImoduleisnotused . Twooperationalmodes:masterandslave Datawordlength:onetosixteendatabits Fourclockingschemes(controlledbyclockpol arityandclockphasebits)include: Simultaneousreceiveandtransmitoperation( transmitfunctioncanbedisabledinsoftware) (SPI)SPRUEU3A August2008 12 ,theregisterdataisinthelowerbyte(7 0),andtheupperbyte(15 8) : 16-leveltransmit/receiveFIFO DelayedtransmitcontrolSPRUEU3A August2008 RevisedJune2009 SerialPeripheralInterface(SPI) INT FLAGSPI Bit RateState ControlSPIRXBUFB uffer RegisterClockPhaseReceiverOverrun CharSPISIMOSPISOMI*SPICLKSW2 SMMSSW3To CPUMSW1 SPITXBUFB uffer RegisterRX FIFO _0RX FIFO _1 RX FIFO _15TX FIFO registersTX FIFO _0TX FIFO _1 TX FIFO _15RX FIFO registers161616TX InterruptLogicRX InterruptLogicSPIFFOVF FIFO InterruptRX FIFO / SPIRXINTSPITX / SPITXINTSPISTE , (SPI)SPRUEU3A August2008 ,masteroutSPISOMISPI slaveout,masterinSPISTESPI slavetransmitenableControlSPIC lockRateLSPCLKI nterruptsignalsSPIRXINTT ransmitinterrupt/ReceiveInterruptinnonFI FO mode(referredtoasSPIINT)Receiveininterru ptinFIFO modeSPITXINTT ransmitinterrupt (x16)

6 DescriptionSPICCR0x0000-70401 SPIC onfigurationControlRegisterSPICTL0x0000- 70411 SPIO perationControlRegisterSPIST0x0000-70421 SPIS tatusRegisterSPIBRR0x0000-70441 SPIBaudRateRegisterSPIEMU0x0000-70461 SPIE mulationBufferRegisterSPIRXBUF0x0000-704 71 SPIS erialInputBufferRegisterSPITXBUF0x0000-7 0481 SPIS erialOutputBufferRegisterSPIDAT0x0000-70 491 SPIS erialDataRegisterSPIFFTX0x0000-704A1 SPIFIFOT ransmitRegisterSPIFFRX0x0000-704B1 SPIFIFOR eceiveRegisterSPIFFCT0x0000-704C1 SPIFIFOC ontrolRegisterSPIPRI0x0000-704F1 SPIP riorityControlRegisterThisSPIhas16-bittr ansmitandreceivecapability, ,SPIDAT(andthenewtransmitbuffer,SPITXBUF ), ,alongwiththeassociatedregisters,SPIPC1( 704Dh)andSPIPC2(704Eh).Thesebitsarenowin theGeneral- : SPICCR(SPIconfigurationcontrolregister). ContainscontrolbitsusedforSPIconfigurati on SPImodulesoftwarereset SPICLK polarityselection FourSPIcharacter-lengthcontrolbitsSPRUEU 3A August2008 RevisedJune2009 SerialPeripheralInterface(SPI) SPICTL(SPIoperationcontrolregister).

7 Containscontrolbitsfordatatransmission TwoSPIinterruptenablebits SPICLK phaseselection Operationalmode(master/slave) Datatransmissionenable SPISTS(SPIstatusregister).Containstworec eivebufferstatusbitsandonetransmitbuffer statusbit RECEIVEROVERRUN SPIINTFLAG TXBUFFULLFLAG SPIBRR(SPIbaudrateregister).Containsseve nbitsthatdeterminethebittransferrate SPIRXEMU(SPIreceiveemulationbufferregist er). SPIRXBUF(SPIreceivebuffer theserialreceivebufferregister).Contains thereceiveddata SPITXBUF(SPItransmitbuffer theserialtransmitbufferregister).Contain sthenextcharactertobetransmitted SPIDAT(SPIdataregister).Containsdatatobe transmittedbytheSPI, ,abitfromthereceivebitstreamisshiftedint otheotherendoftheshiftregister SPIPRI(SPIpriorityregister).Containsbits thatspecifyinterruptpriorityanddetermine SPIoperationontheXDS ,interrupts,dataformat,clocksources, , ( )ishigh,dataistransmittedandreceivedahal f-cyclebeforetheSPICLK transition( ).

8 Asaresult, : Mastersendsdata;slavesendsdummydata. Mastersendsdata;slavesendsdata. Mastersendsdummydata; ,however, (SPI)14 SPRUEU3A August2008 RevisedJune2009 SubmitDocumentationFeedbackSPI master (master/slave = 1)SPI slave (master/slave = 0) 0 Serial input bufferSPIRXBUFS hift register(SPIDAT) 0 Serial transmit bufferSPITXBUFP rocessor 0 SPICLKSPISOMISPISTESPISIMOSPICLKSPISOMIS PISTESPISIMOS lave in/master outSPIstrobeSlave out/master 0 Serial input bufferSPIRXBUFS hift register(SPIDAT) 0 Serial transmit 0 Processor ( ) (MASTER/SLAVE=1), ,MSB(mostsignificantbit) ,receiveddataisshiftedthroughtheSPISOMI pinintotheLSB(leastsignificantbit) ,thereceiveddataistransferredtotheSPIRXB UF(bufferedreceiver) ,thefollowingeventsoccur: SPIDAT contentsaretransferredtoSPIRXBUF. SPIINTFLAGbit( )issetto1. IfthereisvaliddatainthetransmitbufferSPI TXBUF,asindicatedbytheTXBUFFULL bitinSPISTS,thisdataistransferredtoSPIDA T andistransmitted;otherwise,SPICLK stopsafterallbitshavebeenshiftedoutofSPI DAT.

9 IftheSPIINTENAbit( )issetto1, , (MASTER/SLAVE=0), , August2008 RevisedJune2009 SerialPeripheralInterface(SPI) ( ) ( ) , , ,andSPITXBUF hasnotbeenpreviouslyloaded, ( )iscleared,datatransmissionisdisabled,an dtheoutputline(SPISOMI) , , ; , ,dataformat,clocking,initialization, : SPIINTENAbit( ) SPIINTFLAGbit( ) OVERRUNINTENAbit( ) RECEIVEROVERRUNFLAGbit( )WhentheSPIinterrupt-enablebitissetandan interruptconditionoccurs, ,theSPIINTFLAGbit( )isset,andaninterruptisgeneratedifenable dbytheSPIINTENAbit( ).Theinterruptflagremainssetuntilitiscle aredbyoneofthefollowingevents: Theinterruptisacknowledged(thisisdiffere ntfromtheC240). TheCPUreadstheSPIRXBUF(readingtheSPIRXEM U doesnotcleartheSPIINTFLAGbit). ThedeviceentersIDLE2orHALT modewithanIDLE instruction. SoftwareclearstheSPISWRESETbit( ). (SPI)SPRUEU3A August2008 ( ) ( ) , ,thenewcharacteriswrittenintoSPIRXBUF,an dtheRECEIVEROVERRUNF lagbit( ) ( ) ( ) ( 0)specifythenumberofbits(1to16) : Datamustbeleft-justifiedwhenwrittentoSPI DATandSPITXBUF.

10 DatareadbackfromSPIRXBUF isright-justified. SPIRXBUF containsthemostrecentlyreceivedcharacter ,right-justified,plusanybitsthatremainfr omprevioustransmission(s)thathavebeenshi ftedtotheleft(showninExample1-1). ( 0) (beforetransmission)0111001101111011 SPIDAT(aftertransmission)(TXed)0 111001101111011x(1) (RXed)SPIRXBUF(aftertransmission)1110011 01111011x(1)(1)x=1ifSPISOMI dataishigh;x=0ifSPISOMI dataislow; August2008 RevisedJune2009 SerialPeripheralInterface(SPI) Baud RateLSPCLK(SPIBRR1)=+(1-1)SPI Baud RateLSPCLK4=(1-2)Maximum SPI Baud RateLSPCLK440106410106bps=== (1-3) ,theSPICLK pincanreceiveanexternalSPIclocksignalorp rovidetheSPIclocksignal,respectively. Intheslavemode,theSPIclockisreceivedonth eSPICLK pinfromtheexternalsource,andcanbenogreat erthantheLSPCLK frequencydividedby4. Inthemastermode,theSPIclockisgeneratedby theSPIandisoutputontheSPICLKpin, :ForSPIBRR=0,1,or2:where:LSPCLK=Low-spee dperipheralclockfrequencyofthedeviceSPIB RR=ContentsoftheSPIBRR inthemasterSPIdeviceTodeterminewhatvalue toloadintoSPIBRR,youmustknowthedevicesys temclock(LSPCLK)frequency(whichisdevice- specific) ( )andtheCLOCKPHASEbit( ) ,eitherrisingorfalling, : (SPI)SPRUEU3A August2008 RevisedJune2009 SubmitDocumentationFeedbackSPICLK cyclenumber12345678 SPICLK(Falling edgewithout delay)SPICLK(Falling edgewith delay)SPISIMO/SPISOMISPISTEMSBLSBNote:Pr evious data bit(Into slave)Receive latch pointsSPICLK(Rising edgewithout delay)SPICLK(Rising edgewith delay)See noteCLKOUTSPICLK2 cycles3 cycles2 ( )( ) ,SPICLK symmetryisretainedonlywhentheresultof(SP IBRR+1) (SPIBRR+1)isanoddvalueandSPIBRR isgreaterthan3, (0).