Understanding Microchip s CAN Module Bit Timing

1 2001 Microchip Technology 1 MAN754 INTRODUCTIONThe Controller Area Network (CAN) protocol is anasynchronous serial bus with Non-Return to Zero(NRZ) bit coding designed for fast, robust communica-tions in harsh environments, such as automotive andindustrial applications. The CAN protocol allows theuser to program the bit rate, the sample point of the bit,and the number of times the bit is sampled. With thesefeatures, the network can be optimized for a are relationships between bit Timing parameters,the physical bus propagation delays, and the oscillatortolerances throughout the system. This applicationnote investigates these relationships as they pertain toMicrochip s CAN Module and assists in optimizing thebit Timing for given physical system CAN BIT TIMEThe CAN bit time is made up of non-overlapping seg-ments. Each of these segments are made up of integerunits called Time Quanta (TQ) and are explained laterin this application note.

2 The Nominal Bit Rate (NBR) isdefined in the CAN specification as the number of bitsper second transmitted by an ideal transmitter with noresynchronization and can be described with theequation:Nominal Bit TimeThe Nominal Bit Time (NBT), or tbit, is made up of non-overlapping segments (Figure 1), therefore, the NBT isthe summation of the following segments:Associated with the NBT are the Sample Point, Syn-chronization Jump Width (SJW), and Information Pro-cessing Time (IPT), which are explained SEGMENTThe Synchronization Segment (SyncSeg) is the firstsegment in the NBT and is used to synchronize thenodes on the bus. Bit edges are expected to occurwithin the SyncSeg. This segment is fixed at SEGMENTThe Propagation Segment (PropSeg) exists to com-pensate for physical delays between nodes. The prop-agation delay is defined as twice the sum of the signal spropagation time on the bus line, including the delaysassociated with the bus driver.

3 The PropSeg is pro-grammable from 1 - SEGMENT 1 AND PHASE SEGMENT 2 The two phase segments, PS1 and PS2 are used tocompensate for edge phase errors on the bus. PS1 canbe lengthened or PS2 can be shortened by resyncroni-zation. PS1 is programmable from 1 - 8TQ and PS2 isprogrammable from 2 - 1:CAN BIT TIME SEGMENTSA uthor:Pat RichardsMicrochip Technology fbit1tbit-------==tbittSyncSegtPropSegtP S1tPS2+++=Nominal Bit Time (NBT), tbitSamplePointSyncSegPropSegPhaseSeg1 (PS1)PhaseSeg2 (PS2) Understanding Microchip s CAN Module Bit TimingAN754DS00754A-page 2 2001 Microchip Technology POINTThe sample point is the point in the bit time in which thelogic level is read and interpreted. The sample point islocated at the end of phase segment 1. The exceptionto this rule is, if the sample mode is configured to sam-ple three times per bit. In this case, the bit is still sam-pled at the end of PS1, however, two additionalsamples are taken at one-half TQ intervals prior to theend of PS1 and the value of the bit is determined by amajority PROCESSING TIMEThe Information Processing Time (IPT) is the timerequired for the logic to determine the bit level of a sam-pled bit.

4 The IPT begins at the sample point, is mea-sured in TQ and is fixed at 2TQ for the Microchip CANmodule. Since phase segment 2 also begins at thesample point and is the last segment in the bit time, it isrequired that PS2 minimum is not less than the :SYNCHRONIZATION JUMP WIDTHThe Synchronization Jump Width (SJW) adjusts the bitclock as necessary by 1 - 4TQ (as configured) to main-tain synchronization with the transmitted on synchronization is covered QuantumEach of the segments that make up a bit time are madeup of integer units called Time Quanta (TQ). The lengthof each Time Quantum is based on the oscillator period(tOSC). The base TQ equals twice the oscillator 2 shows how the bit period is derived from TOSCand TQ. The TQ length equals one TQ Clock period(tBRPCLK), which is programmable using a programma-ble prescaler named the Baud Rate Prescaler (BRP).This is shown in the following equation:Where: BRP equals the configuration as shown inFigure Timing Control RegistersThe CAN Bit Timing Control (CNF) registers are thethree registers that configure the CAN bit time.

5 Figure 3details the function of the CNF adjusting the length of the TQ (tTQ) and the numberof TQs in each segment, both the nominal bit time andthe sample point can easily be configured as THE Timing SEGMENTSThe are several requirements for programming theCAN bit Timing + PS1 + PS1 > SJWFIGURE 2:TQ AND THE BIT PERIODPS2minIPT 2TQ==TQ 2 BRP TOSC2 BRP FOSC-------------------= =toscTBRPCLKtBITSync(fixed)PropSeg(Progr ammable)PS2(Programmable)PS1(Programmabl e)TQ(tTQ)CAN Bit Time 2001 Microchip Technology 3AN754 FIGURE 3:CAN BIT Timing CONTROL REGISTERS (MCP2510 CNF REGISTERS) 7bit 7bit 7bit 0---WAKFILPHSEG22---PHSEG20 SJW<1:0> (Synchronization Jump Width Length as measured in TQ):11 = 4TQ10 = 3TQ01 = 2TQ00 = 1 TQBRP<5:0> (Baud Rate Prescaler TQ length as a multiple of tosc)111111 = TQ = 2 x 64 x tOSC..000010 = TQ = 2 x 3 x tOSC000001 = TQ = 2 x 2 x tOSC000000 = TQ = 2 x 1 x tOSCBTLMODE (Determines how PS2 is calculated)1 = PS2 is determined by <2:0>0 = PS2 is the greater of PS1 and the Information Processing Time (IPT)SAM (Configures the sample point as one sample or three samples1 = Sample three times per bit0 = Sample once per bitPS1<2:0> (Configures Phase Segment 1)111 = 8TQ.)

6 001 = 2TQ000 = 1 TQPRSEG<2:0> (Configures the Propagation Segment)111 = 8TQ..001 = 2TQ000 = 1 TQWAKFIL (Enables/Disables the wakeup filter)1 = Filter enabled0 = Filter disabledPS2<2:0> (Configures Phase Segment 2)111 = 8TQ..001 = 2TQ000 = Not Valid (PS2 MIN = IPT = 2TQ)CNF1 CNF3 CNF2AN754DS00754A-page 4 2001 Microchip Technology THE BIT TIMEAll nodes on the CAN bus must have the same nominalbit rate. Noise, phase shifts, and oscillator drift createsituations where the nominal bit rate does not equal theactual bit rate in a real system. Therefore, the nodesmust have a method for achieving and maintaining syn-chronization with bus ToleranceThe bit Timing for each node in a CAN system is derivedfrom the reference frequency (fOSC) of its node. Thiscreates a situation where phase shifting and oscillatordrift will occur between nodes due to less than idealoscillator tolerances between the CAN specification indicates that the worst caseoscillator tolerance is and is only suitable for lowbit rates (125 kb/s or less).

7 This application note doesnot cover oscillator tolerances in detail, however, thereferences at the end of this application note providemore information on the DelayThe CAN protocol has defined a recessive (logic 1) anddominant (logic 0) state to implement a non-destructivebit-wise arbitration scheme. It is this arbitration method-ology that is affected the most by propagation node involved with arbitration must be able tosample each bit level within the same bit time. Forexample, if two nodes at opposite ends of the bus startto transmit their messages at the same time, they mustarbitrate for control of the bus. This arbitration is onlyeffective if both nodes are able to sample during thesame bit time. Figure 4 shows a one-way propagationdelay between two nodes. Extreme propagation delays(beyond the sample point) will result in invalid arbitra-tion. This implies that bus lengths are limited at givenCAN data CAN system s propagation delay is calculated asbeing a signal s round trip time on the physical bus(tbus), the output driver delay (tdrv), and the input com-parator delay (tcmp).

8 Assuming all nodes in the systemhave similar component delays, the propagation delayis explained mathematically as:SynchronizationAll nodes on a given CAN bus must have the sameNBT. The NRZ bit coding does not encode a clock intothe message. The receivers must synchronize to thetransmitted data stream to insure messages are prop-erly decoded. There are two methods used for achiev-ing and maintaining SYNCHRONIZATIONHard Synchronization only occurs on the first reces-sive-to-dominant (logic 1 to 0 ) edge during a bus idlecondition, which indicates a Start-of-Frame (SOF) con-dition. Hard synchronization causes the bit timingcounter to be reset to the SyncSeg which causes theedge to lie within the SyncSeg. At this point, all of thereceivers will be synchronized to the synchronization occurs only once during a mes-sage. Also, resynchronization may not occur during thesame bit time (SOF) that hard ++() = 2001 Microchip Technology 5AN754 FIGURE 4:ONE WAY PROPAGATION DELAYSyncSegPropSegPhaseSeg1 (PS1)PhaseSeg2 (PS2)SamplePointSyncSegPropSegPhaseSeg1 (PS1)PhaseSeg2 (PS2)Transmitted Bit from Node A Node A bit received by Node B Propagation DelayTime (t)AN754DS00754A-page 6 2001 Microchip Technology is implemented to maintain the ini-tial synchronization that was established by the hardsynchronization.

9 Without resynchronization, the receiv-ing nodes could get out of synchronization due to oscil-lator drift between is achieved by implementing a Dig-ital Phase Lock Loop (DPLL) function which comparesthe actual position of a recessive-to-dominant edge onthe bus to the position of the expected edge (within theSyncSeg) and adjusting the bit time as phase error of a bit is given by the position of theedge in relation to the SyncSeg, measured in TQ, andis defined as follows: e = 0; the edge lies within the SyncSeg. e > 0; the edge lies before the sample point. (TQ added to PS1). e < 0; the edge lies after the sample point of the previous bit. (TQ subtracted from PS2)FIGURE 5:SYNCHRONIZING THE BIT TIMESyncSegPropSegPhaseSeg1 (PS1)PhaseSeg2 (PS2)SamplePointSyncSegPropSegPhaseSeg1 (PS1)PhaseSeg2 (PS2)SamplePointSyncSegPropSegPhaseSeg1 (PS1)PhaseSeg2 (PS2)SamplePointNominal Bit Time (NBT)SJW (PS1)SJW (PS2)Nominal Bit Time (NBT)SJW (PS1)SJW (PS2)Actual Bit TimeResynchronization to a Slower Transmitter (e > 0)Input SignalInput Signal (e < 0)SJW (PS1)SJW (PS2)Nominal Bit Time (NBT)Actual Bit TimeResynchronization to a Faster Transmitter (e < 0)Input Signal (e = 0)No Resynchronization (e = 0)(e > 0)

10 2001 Microchip Technology 7AN754 Figure 5 shows how phase errors, other than zero,cause the bit time to be lengthened or recessive-to-dominant edges will be usedfor one synchronization within one bit time edge will be used for synchronization only ifthe value at the previous sample point differsfrom the bus value immediately after the transmitting node will not resynchronize on apositive phase error (e > 0). This implies that atransmitter will not resynchronize due to propa-gation delays of it s own transmitted receivers will synchronize the absolute magnitude of the phase error isgreater than the SJW, then the appropriatephase segment will be adjusted by an amountequal to the IT ALL TOGETHERAs indicated previously, the CAN protocol implementsa non-destructive bitwise arbitration scheme thatallows multiple nodes to arbitrate for control of the , it is necessary for all the nodes to detect/sample the bits within the same bit time.