Using IBIS Models for Timing Analysis (Rev. A) - …

1 Application ReportSPRA839A - April 20031 Using ibis Models for Timing AnalysisC6000 Hardware ApplicationsABSTRACTT oday s high-speed interfaces require strict timings and accurate system design . To achievethe necessary timings for a given system, input/output buffer information specification ( ibis ) Models must be used. These Models accurately represent the device drivers under variousprocess conditions. Board characteristics, such as impedance, loading, length, number ofnodes, etc., affect how the device driver behaves. This application report discusses how toproperly use ibis Models to attain accurate Timing Analysis for a given system. This reportfocuses on the use of SDRAM with a TMS320C6000 DSP, but is applicable to all interfacesthat have setup and hold .. 2 Establishing a Reference Point3.. 3 Understanding the Tester5.. Tester Load Adjustment5.. Using Data Sheet Timing on a Real System Board7.. Variations Between Device Pins9.. 4 The Reference Voltage10.

2 Understanding Vref Measured on Tester vs. Real Board11.. Translating Data Sheet Reference Voltage From Vref to VIL/VIH11.. 5 Noise Margins12.. 6 ibis Calculation Methods13.. Input Setup of the SDRAM14.. Input Hold of the SDRAM16.. Input Setup of the DSP17.. Input Hold of the DSP19.. 7 Summary of AC Timing Analysis Procedures20.. Gathering Information20.. ibis Simulations21.. ibis Simulations for DSP Outputs on the Board21.. ibis Simulations for DSP Outputs With Test Load21.. ibis Simulations for SDRAM Outputs on the Board22.. ibis Simulations for SDRAM Outputs With Test Load22.. Calculations23.. Input Setup of the SDRAM23.. Input Hold of the SDRAM24.. Input Setup of the DSP24.. Input Hold of the DSP24.. 8 Conclusion25.. Trademarks are the property of their respective ibis Models for Timing AnalysisList of FiguresFigure 1. DSP Writes (Control Signals and/or Data Signals)4.

3 Figure 2. DSP Reads (Data Signals Only)4.. Figure 3. Board Route/Loading vs Tester Route/Loading5.. Figure 4. Signal Delay With Heavier Load Than Tester Load (C0 < A0)6.. Figure 5. Signal Delay With Lighter Load Than Tester Load (C0 > A0)7.. Figure 6. Data Sheet Timing8.. Figure 7. Adding Tester Load Adjustment to Obtain Timing at SDRAM9.. Figure 8. Interpolation Using Vref10.. Figure 9. Difficulty in Defining Single (tref, Vref) on Boards Without Clean Waveforms11.. Figure 10. Translating Input Requirement to VIL/VIH Reference Volage12.. Figure 11. Noise Margin for a Typical Signal13.. Figure 12. Input Setup of the SDRAM15.. Figure 13. Input Hold of the SDRAM17.. Figure 14. Input Setup of the DSP18.. Figure 15. Input Hold of the DSP20.. Figure 16. Example DSP-SDRAM Interface Board Characteristics20.. Figure 17. ibis Representation of DSP Output on a Board21.. Figure 18. ibis Representation of DSP Output With Test Load21.. Figure 19.

4 ibis Representation of SDRAM Output on a Board22.. Figure 20. ibis Representation of SDRAM Output With Test Load23.. List of TablesTable 1. SDRAM Input Setup Parameters15.. Table 2. SDRAM Input Hold Parameters16.. Table 3. DSP Input Setup Parameters18.. Table 4. DSP Input Hold Parameters19.. 1 IntroductionDigital signal processors (DSPs) and memories are tested to specifications given by theirrespective data sheets. These tests are performed under specific operating conditions given bythe data sheets. Any variation from these specific operating conditions will cause a change inbehavior from which the device was tested. These operating conditions include temperature,voltage, frequency, capacitive loading, impedance, buffer information specification ( ibis ) is a fast and accurate way of modeling abuffer s behavior over all process conditions. ibis Models are generated based on V/I curvesderived from full-circuit simulations and/or bench-top testing.

5 In order to use ibis Models , asimulation package, from companies such as Hyperlynx or Mentor Graphics, must bepurchased. These simulation packages give accurate information on signal integrity issues thatmay occur based on system, board, and component-level example, a DSP tester has a given test load. If a board has more or less loading than that ofthe tester, the timings will be skewed from what was originally intended. This can hurt or help thesystem, depending on which way the Timing is skewed, and what parameter is of Using ibis Models for Timing AnalysisImportant to this application report is that of impedance and loading. It is assumed thatfrequency remains constant, the voltage remains well within the data sheet specification range,and the temperature remains at or near room condition (well within the specification limits,normally 0_C and 90_C).Systems that use multiple sychronous dynamic random-access memory (SDRAM) chips to fillthe bus width will have to do ibis simulations on each component.

6 This must be done sincethere is no longer a point-to-point connection between the DSP and the SDRAM. The variationsin trace lengths create differences in timings between the multiple components. Users mustperform ibis simulations to ensure signal application report discusses the various reference points for timings that are important toboth the DSP and the SDRAM. In section 3, an overview of the tester used to test the DSPand/or the SDRAM is given along with an explanation of the Timing variation between the testerand a typical board. Reference voltages and noise margins impact the timings presented by boththe tester and a typical board. An understanding of why this occurs is briefly discussed insections 4 and 5. Section 6 of this application report encompasses the formulas used toestablish setup and hold times for both the DSP and the SDRAM, based on ibis 7 summarizes the AC Timing Analysis a Reference PointData sheet timings are measured from the pins of the device connected to the test board with agiven tester load.

7 On a real system board, these timings change as loading increases ordecreases from the loading on the tester board. Before going into further details (in section 3) onhow timings differ on a real system board versus the test board, this section discusses how toestablish a reference point. A reference point must be established when modeling a board thatvaries from the original test board model . As a matter of convenience, the reference point istaken from just inside the master device, the DSP. The reference point represents the time inwhich the DSP output buffer is 1 gives a high-level drawing of how a DSP write to SDRAM can be represented in a realsystem board. The point, denoted by t0, is the point in which all timings will be referenced. Thepoints A, B, D, and E are measured at the pins of the DSP and SDRAM, respectively. Point Fdescribes the point at which the output buffer turns on relative to time t0. Xn is an internal timingdelay that is represented by a constant value, fixed by the design of the DSP.

8 Assume that thedesign of the DSP sets Xn to ns. Also assume that the output buffer at A had an internaldelay of ns, and the output buffer at D had an internal delay of ns. Calculations wouldshow that the time at point A is (t0 + ) ns, or simply ns relative to t0, Similarly, calculationswould show that the time at point D is (t0 + Xn + ) ns = (t0 + ) ns, or simply nsrelative to t0. The output setup time for the DSP is calculated from when the data transitions atpoint D, to when the clock transitions at point A. In this case, the output setup time is [ ( )] ns = 3 will be different for hold times, since this uses different internal logic to gate the ibis Models for Timing AnalysisSDRAMD igital Signal ProcessorBAFDEC ontrol / DataEMIF Clockt0 XnFigure 1. DSP Writes (Control Signals and/or Data Signals)In the case of DSP reads, the DSP outputs the clock, control, and address signals as shown inFigure 1. Upon receiving the read command, the SDRAM outputs the data signals.

9 Figure 2gives a high-level drawing of how the SDRAM outputs data relative to the clock from the represents the internal Timing delay generated by the SDRAM. The SDRAM measures inputand output timings with respect to the clock signal at the pin of the device. For example, theoutput hold time of the SDRAM starts as soon as the clock signal at point B passes a givenreference voltage, Vref. The hold time ends at point D as soon as the signal crosses that the output hold design of the SDRAM sets Yn to ns. Also assume that the inputbuffer at B has a delay of ns, and the output buffer at D has a delay of ns. Calculationswould show that, in Figure 2, the time at point D relative to point B is [ + Yn + ] ns = [ + + ] = ns, giving an SDRAM output hold time of ns in this Signal ProcessorBAFDEDataEMIF Clockt0 YnFigure 2. DSP Reads (Data Signals Only)SPRA839A5 Using ibis Models for Timing AnalysisBoth the DSP and the SDRAM measure input and output timings with respect to the clock signalat the pin of the device.

10 Output times are measured when Vref is crossed at the data/controlsignal relative to when Vref is crossed at the clock. Input times are measured when thedata/control signal goes valid (setup times) or invalid (hold times) relative to when Vref is crossedat the the Load AdjustmentAs mentioned in previous sections, the tester loading must be accounted for when performingtiming Analysis on a real system board. The tester loading must be subtracted out of the boardroutes in order to accurately reflect the change in loading. Figure 3 gives a simplistic view of howthe board route varies from the tester (see Note)Tester load circuitCTransmission lineCrefTypical point-to-point board routeTypical tester routet0t0 NOTE: Tester load circuit differs on the various devices. Refer to the device data sheet for the exact tester load 3. Board Route/Loading vs Tester Route/LoadingIn Figure 3, the top figure shows a typical point-to-point board route. The output from the DSP(point A) drives a load consisting of the transmission line and the load at point B.