William Stallings Computer Organization and …

1 + William Stallings Computer Organization and Architecture10thEdition 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.+ Chapter 5 Internal Memory 2016 Pearson Education, Inc., Hoboken, NJ. All rights inControl(a) WriteCellSelectSenseFigure Memory Cell OperationControl(b) Read 2016 Pearson Education, Inc., Hoboken, NJ. All rights Semiconductor Memory TypesMemory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile Read-only memory (ROM) Masks Programmable ROM (PROM) Read-only memory Not possible Erasable PROM (EPROM) UV light, chip-level Electrically Erasable PROM (EEPROM) Electrically, byte-level Flash memory Read-mostly memory Electrically, block-level Electrically Nonvolatile 2016 Pearson Education, Inc.

2 , Hoboken, NJ. All rights reserved.+Dynamic RAM (DRAM) RAM technology is divided into two technologies: Dynamic RAM (DRAM) Static RAM (SRAM) DRAM Made with cells that store data as charge on capacitors Presence or absence of charge in a capacitor is interpreted as a binary 1 or 0 Requires periodic charge refreshing to maintain data storage The term dynamic refers to tendency of the stored charge to leak away, even with power continuously applied 2016 Pearson Education, Inc., Hoboken, NJ. All rights lineGrounddc voltageAddressline(b) Static RAM (SRAM) cellFigure Typical Memory Cell Structures(a) Dynamic RAM (DRAM) cellBit lineBC1T1T2T3T5T6T4C2 Bit lineBBit lineBTransistorGroundStoragecapacitor 2016 Pearson Education, Inc.

3 , Hoboken, NJ. All rights INDICATES STATE WHEN A BINARY 1 +Static RAM (SRAM) Digital device that uses the same logic elements used in the processor Binary values are stored using traditional flip-flop logic gate configurations Will hold its data as long as power is supplied to it 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.+ SRAM versusDRAM Both volatile Power must be continuously supplied to the memory to preserve the bit values Dynamic cell Simpler to build, smaller More dense (smaller cells = more cells per unit area) Less expensive Requires the supporting refresh circuitry Tend to be favored for large memory requirements Used for main memory Static Faster Used for cache memory (both on and off chip)SRAMDRAM 2016 Pearson Education, Inc.

4 , Hoboken, NJ. All rights reserved.+Read Only Memory (ROM) Contains a permanent pattern of data that cannot be changed or added to No power source is required to maintain the bit values in memory Data or program is permanently in main memory and never needs to be loaded from a secondary storage device Data is actually wired into the chip as part of the fabrication process Disadvantages of this: No room for error, if one bit is wrong the whole batch of ROMs must be thrown out Data insertion step includes a relatively large fixed cost 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.+Programmable ROM (PROM) Less expensive alternative Nonvolatile and may be written into only once Writing process is performed electrically and may be performed by supplier or customer at a time later than the original chip fabrication Special equipment is required for the writing process Provides flexibility and convenience Attractive for high volume production runs 2016 Pearson Education, Inc.

5 , Hoboken, NJ. All rights -Mostly MemoryEPROME rasable programmable read-only memoryErasure process can be performed repeatedlyMore expensive than PROM but it has the advantage of the multiple update capability EEPROME lectrically erasable programmable read-only memoryCan be written into at any time without erasing prior contentsCombines the advantage of non-volatility with the flexibility of being updatable in placeMore expensive than EPROM Flash MemoryIntermediate between EPROM and EEPROM in both cost and functionalityUses an electrical erasing technology, does not provide byte-level erasureMicrochip is organized so that a section of memory cells are erased in a single action or flash 2016 Pearson Education, Inc.

6 , Hoboken, NJ. All rights DecoderRefresh circuitryMemory array(2048 2048 4)RowDe-coderA0A1A10 RowAddressBufferColumnAddressBufferTimin g and ControlRASCASWEOEMUXR efreshCounterData InputBufferData OutputBufferD1D2D3D4 Figure Typical 16 Megabit DRAM (4M 4) 2016 Pearson Education, Inc., Hoboken, NJ. All rights as four squarearrays of 2048 by 2048 of the array areconnected by bothhorizontal (row)and vertical(column) line connects to theSelect terminal of each cell in itsrowVertical line connects to the Data-In/Sense terminal of eachcell in its involves stepping through each row, reading the cells with RAS and then writing them right back.

7 2016 Pearson Education, Inc., Hoboken, NJ. All rights -8 DecoderINVERTERAND 2016 Pearson Education, Inc., Hoboken, NJ. All rights MultiplexerINVERTERANDORF=D0+D1+D2+D34M 424 Pin "Top ViewFigure Typical Memory Package Pins and Signals323130292827262524232221201918171 2345678910111213141516A19A16A15A12A7A6A5 A4A3A2A1A0D0D1D2 VssVccA18A17A14A13A8A9A11 VppA10 CED7D6D5D4D332 Pin "Top View1M 8242322212019181716151413123456789101112 VccD0D1 WERASNCA10A0A1A2A3 VccVssD3D2 CASOEA9A8A7A6A5A4 Vss(a) 8 Mbit EPROM(b) 16 Mbit DRAM 2016 Pearson Education, Inc., Hoboken, NJ. All rights words by512 bitsChip #1 Memory bufferregister (MBR)Figure 256-KByte Memory OrganizationMemory addressregister (MAR)Decode 1 of512 bit-senseDecode 1 of512512 words by512 bitsChip #8 Decode 1 of512 bit-senseDecode 1 of5121992345678 2016 Pearson Education, Inc.

8 , Hoboken, NJ. All rights reserved.+ 2016 Pearson Education, Inc., Hoboken, NJ. All rights MemoryComposed of a collection of DRAM chipsGrouped together to form a memory bankEach bank is independently able to service a memory read or write requestKbanks can service Krequests simultaneously, increasing memory read or write rates by a factor of KIf consecutive words of memory are stored in different banks, the transfer of a block of memory is speeded up 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.+Error Correction Hard Failure Permanent physical defect Memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1 Can be caused by: Harsh environmental abuse Manufacturing defects Wear Soft Error Random, non-destructive event that alters the contents of one or more memory cells No permanent damage to memory Can be caused by: Power supply problems Alpha particles 2016 Pearson Education, Inc.

9 , Hoboken, NJ. All rights Error-Correcting Code FunctionData InData OutError SignalMKMMKK 2016 Pearson Education, Inc., Hoboken, NJ. All rights 11000(d)(c)01 110000 Figure Hamming Error-Correcting Code1 11001(b)(a)01 ABCABCABCABC101 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. Single-Error Correction Single-Error Correction/ Double-Error Detection Data Bits Check Bits % Increase Check Bits % Increase 8 4 50 5 16 5 6 32 6 7 64 7 8 128 8 9 256 9 10 Table Increase in Word Length with Error Correction 2016 Pearson Education, Inc., Hoboken, NJ. All rights Position 12 11 10 9 8 7 6 5 4 3 2 1 Position Number 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 Data Bit D8 D7 D6 D5 D4 D3 D2 D1 Check Bit C8 C4 C2 C1 Figure Layout of Data Bits and Check Bits 2016 Pearson Education, Inc.

10 , Hoboken, NJ. All rights reserved. 2016 Pearson Education, Inc., Hoboken, NJ. All rights = D1 D2 D4 D5 D7C2 = D1 D3 D4 D6 D7C4 = D2 D3 D4 D8C8 = D5 D6 D7 D8 Hamming Codes - SEC Bit position 12 11 10 9 8 7 6 5 4 3 2 1 Position number 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 Data bit D8 D7 D6 D5 D4 D3 D2 D1 Check bit C8 C4 C2 C1 Word stored as 0 0 1 1 0 1 0 0 1 1 1 1 Word fetched as 0 0 1 1 0 1 1 0 1 1 1 1 Position Number