Transcription of ASIC Physical Design Standard-Cell Design Flow
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ASIC Physical Design Standard-Cell Design Flow
ASIC Physical DesignStandard-Cell Design FlowUsing the Cadence InnovusDigital Implementation SystemASIC Physical Design (Standard Cell)(can also do full custom layout)FloorplanChip/BlockPlace & RouteStd. CellsComponent-Level Verilog NetlistIC Mask DataDesign RuleCheckStd. CellLayoutsCadence Innovus Digital Implementation SystemADiT/Eldo Simulation ModelBackannotateSchematicGenerateMask DataLayout RulesProcess DataLibrariesCalibreCalibreCalibreNetlis t-to-layoutdesign flowSynopsys JupiterXT Cadence SOC Innovus InnovusDigital Implementation (EDI) System GUIEDI Design flowFloorplan ( flat ) through implementationDesign Import (specify input files)File > Design ImportGate-level netlist Verilog file(s) Physical data (LEF)Technology CellsIO pin planningPower planningTiming data andconstraintsExecutes init_designcommand to load files Verilog gate-level netlist(s) Gates from the standard cell library Design can be hierarchical or flat Tclcommands.
Ideally perform at three times during the design flow Pre-CTS (clock tree synthesis) – trial route after placing cells Post-CTS – clock tree should improve timing Post-Route – after completed routing timeDesign: create trial route, extract delays, analyze timing, generate reports (reg2reg, in2reg, reg2out)
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