The Delay-Locked Loop
to adjust the delay and force DT toward zero. This conjecture leads us to the arrangement depicted in Figure 2(c ). Here, a phase detector mea-sures the skew and adjusts the delay of B 2 to reduce DT. As with PLLs, the low-pass filter attenuates the high-frequency compo-nents generated by the PD. This circuit exemplifies a simple delay-locked loop.
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