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1. General description - NXP

1. General descriptionThe SJA1105 is an IEEE 5-port automotive ethernet switch. Each of the five ports can be individually configured to operate in MII, RMII and RGMII modes. This arrangement provides the flexibility to connect a mix of switches, microprocessors and PHY devices such as the TJA1100 BroadR-Reach PHY from NXP Semiconductors (Ref. 1 and Ref. 2) and other commercially available Fast ethernet and Gigabit ethernet PHYs. The high-speed interface makes it easy to cascade multiple SJA1105s for scalability. It can be used in various automotive scenarios such as gateway applications, body domain controllers or for interconnecting multiple ECUs in a daisy chain. Audio Video Bridging (AVB) support (Ref. 3) fully leverages infotainment and advanced driver assistance SJA1105 comes in two pin-compatible variants. The SJA1105EL supports ethernet and AVB. The SJA1105 TEL includes additional functionality to support Time-Triggered ethernet (TTEthernet) and Time-Sensitive Networking (TSN).

The SJA1105 is an IEEE 802.3-compliant 5-port automotive Ethernet switch. Each of the five ports can be individually configured to operate in MII, RMII and RGMII modes. ... 100 Mbit/s and RGMII operation at 10 Mbit/s, 100 Mbit/s or 1000 Mbit/s Interface-dependent selectable I/O supply voltages; 1.2 V core voltage Small footprint: LFBGA159 (12 ...

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Transcription of 1. General description - NXP

1 1. General descriptionThe SJA1105 is an IEEE 5-port automotive ethernet switch. Each of the five ports can be individually configured to operate in MII, RMII and RGMII modes. This arrangement provides the flexibility to connect a mix of switches, microprocessors and PHY devices such as the TJA1100 BroadR-Reach PHY from NXP Semiconductors (Ref. 1 and Ref. 2) and other commercially available Fast ethernet and Gigabit ethernet PHYs. The high-speed interface makes it easy to cascade multiple SJA1105s for scalability. It can be used in various automotive scenarios such as gateway applications, body domain controllers or for interconnecting multiple ECUs in a daisy chain. Audio Video Bridging (AVB) support (Ref. 3) fully leverages infotainment and advanced driver assistance SJA1105 comes in two pin-compatible variants. The SJA1105EL supports ethernet and AVB. The SJA1105 TEL includes additional functionality to support Time-Triggered ethernet (TTEthernet) and Time-Sensitive Networking (TSN).

2 2. Features and General features 5-port store and forward architecture Each port individually configurable for MII and RMII operation at 10 Mbit/s or 100 Mbit/s and RGMII operation at 10 Mbit/s, 100 Mbit/s or 1000 Mbit/s Interface-dependent selectable I/O supply voltages; V core voltage Small footprint: LFBGA159 (12 mm 12 mm) package Automotive Grade 2 ambient operating temperature: 40 C to +105 C Automotive product qualification in accordance with ethernet switching and AVB features IEEE compliant 128 kB frame buffer 1024 entry MAC address learning table Address learning space can be configured for static and learned addresses 2 kB frame length handling IEEE defined tag support 4096 VLANs Egress tagging/untagging on a per-VLAN basis per port QoS handling based on IEEE Per-port priority remapping and 8 configurable egress queues per portSJA11055-port automotive ethernet switchRev. 1 7 November 2016 Product data sheetSJA1105 All information provided in this document is subject to legal disclaimers.

3 NXP Semiconductors 2016. All rights data sheetRev. 1 7 November 2016 2 of 34 NXP SemiconductorsSJA11055-port automotive ethernet switch Ingress rate-limiting on a per-port and per-priority basis for Unicast/Multicast and Broadcast traffic Frame replication and retagging of traffic Frame mirroring for enhanced diagnostics Hardware support for IEEE and IEEE for AVB traffic support Ingress and egress timestamping per port Ten IEEE credit-based shapers available; shapers can be freely allocated to any priority queue on a per port basis Support for AVB SR Class A, Class B and Class C traffic IEEE 1588v2 one-step sync forwarding in hardware IEEE support for setting port reachability and disabling address learning Broadcast storm protection Statistics for dropped frames and buffer TT and TSN features (SJA1105 TEL only) IEEE time-aware traffic IEEE per-stream policing (pre-standard) Support for ring-based redundancy (for time-triggered traffic only) 1024 deterministic ethernet flows with per-flow based: Time-triggered traffic transmission Ingress policing and reception window check Active and redundant routes Interface features MII/RMII interfaces supporting all standard ethernet PHY technologies such as (but not limited to) Fast ethernet (IEEE 100 BASE-TX), IEEE 100 BASE-T1 and optical PHYs RGMII for interfacing with Gigabit ethernet ( 1000 BASE-T) PHYs (Gigabit ethernet ; Ref.)

4 4) MAC and PHY modes for interfacing (MII/RMII/RGMII) directly with another switch or host processor Programmable drive strength for all interfaces SPI at up to 25 MHz for host processor Other features 25 MHz system clock input from crystal oscillator or AC-coupled single-ended clock 25 MHz reference clock output Device reset input from host processor IEEE compliant JTAG interface for TAP controller access and boundary scanSJA1105 All information provided in this document is subject to legal disclaimers. NXP Semiconductors 2016. All rights data sheetRev. 1 7 November 2016 3 of 34 NXP SemiconductorsSJA11055-port automotive ethernet switch3. Ordering information 4. Block diagram Table informationType numberPackageNameDescriptionVersionSJA11 05 ELLFBGA159plastic low profile fine-pitch ball grid array package; 159 ballsSOT1427-1 SJA1105 TELFig diagram of SJA1105 ELDDD 63,6/$9(63,67$786 $1' &21752/ 81,7 6&8 /223%$&. 3257 /%3 $8',2 9,'(2 %5,'*,1* $9% 6833257 5; 0$ 0 5; 0$ 0$&3257 [0,,[0,,,138748(8( ,4 9/$1 9/$1B/8 $''5(66 / $''5B/8 32/,&,1* / B32/,&( )25:$5',1* / B)25: 5; 0$ 0$&3257 &*826&,//$725 3//5*87; 0$ 0 7; 0$ 0$ 0$ 0$&3257 '<1$0,& 0(025< 0$1$*(0(17 '00 )5$0( 0(025< &21752//(5 )0& )5$0(%8))(5 0$1$*(0(17 )%0 &6' &&$&8 SJA1105 All information provided in this document is subject to legal disclaimers.)))))))]]

5 NXP Semiconductors 2016. All rights data sheetRev. 1 7 November 2016 4 of 34 NXP SemiconductorsSJA11055-port automotive ethernet switch Fig diagram of SJA1105 TELDDD 63,6/$9(63,67$786 $1' &21752/ 81,7 6&8 /223%$&. 3257 /%3 $8',2 9,'(2 %5,'*,1* $9% 6833257 5; 0$ 0 5; 0$ 0$&3257 [0,,[0,,,138748(8( ,4 9/$1 9/$1B/8 / $''5(66 / $''5B/8 / 32/,&,1* / B32/,&( / )25:$5',1* / B)25: 5; 0$ 0$&3257 &*826&,//$725 3//5*8$ 0$ 0 7; 0$ 0$ 0$ 0$&3257 '<1$0,& 0(025< 0$1$*(0(17 '00 )5$0( 0(025< &21752//(5 )0& )5$0(%8))(5 0$1$*(0(17 )%0 &6' &&9,578$//, ,&,1* 9/B32/,&( 9,578$//,1.)25:$5',1* 9/B)25: 9,578$//, 9/B/8 &/2&. 6<1&+521,=$7,21 68%6<67(0 &66 6&+('8/( (1*,1( 6&+ SJA1105 All information provided in this document is subject to legal disclaimers. NXP Semiconductors 2016. All rights data sheetRev. 1 7 November 2016 5 of 34 NXP SemiconductorsSJA11055-port automotive ethernet switch5. Pinning Pinning Fig configuration diagramDDD WUDQVSDUHQW WRS YLHZEDOO $ LQGH[ DUHD $%&'()*+ )%*$ Fig configuration $9660,, B7;' 0,, B5;B'90,, B5;' 0,, B5;' 0,, B7;' 0,, B7;' %0,, B7;' 0,, B5;' 0,, B5;' 0,, B5;B ' 0,, B7;' &'()*+0,, B7;B( ,, B7;B(5 0,, B5;B(5 0,, B5;B(50,, B7;B B(19660,, B5;B'90,, B5;' 0,, B5;' 0,, B5;' 0,, B5;' 9669660,, B5;B&/.))))))))))))))))]]]

6 017&.9667'2373B&/.6',66B10,, B7;' 0,, B7;B&/.39667066'26 B(50,, B7;' 0,, B7;B(1 DDD 567B10,, B7;' 0,, B7;' 0,, B5;' 0,, B5;' 0,, B5;' 0,, B5;B'99660,, B7;B(50,, B5;' 0,, B5;B(5966966966966966966966966966966966 966966966966966966 966966966966966966 966966966966966966 966966966966966966 9669'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B0,, 9''B&25(9''B&25(9''B&25(9''B&25(9''B&25( 9''B&25(9''B&25(9'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B0,, 9'',2B&/29'',2B+267L F 9''B&25(0,, B7;' 0,, B7;' 0,, B7;B (10,, B5;' 0,, B5;B ' 0,, B5;' 0,, B5;B'90,, B5;' 0,, B7;B(10,, B7;B ' 0,, B7;' 0,, B7;' 0,, B7;' 0,, B5;B(50,, B7;B(50,, B5;' 0,, B5;B'9&/.B2870,, B5;B(59''$B3//966$B3//9''$B26&26&B,126&B 287966$B26 ' 0,, B5;' 0,, B5;B ' 0,, B7;B(10,, B7;B ' 0,, B5;B&/.7567B17',0,, B7;' 0,, B7;' 0,, B7;' 966966 SJA1105 All information provided in this document is subject to legal disclaimers. NXP Semiconductors 2016. All rights data sheetRev.))))))))))))))))))

7 1 7 November 2016 6 of 34 NXP SemiconductorsSJA11055-port automotive ethernet Pin description [1]xMII I/O pins will be floating until the configuration has been loaded.[2]I: digital input; O: digital output; P: power supply. [1]P: power supply; G: description - xMII interface[1]SymbolPinType[2]DescriptionM II interface:01234 VDDIO_MIIxD4 E4 G4D5 D7 D8D10 D11 E11G11 H11 K11L8 L10 V I/O supply voltageTX_CLK/ REF_CLK/TXCD1A7C14K14 N9I/OI/OOTX_CLK: MII interface transmit clock (also configurable as output)REF_CLK: RMII interface reference clock (also configurable as input)TXC: RGMII interface transmit clockTX_EN/ TX_CTLD2B7C13K13 P9 OTX_EN: MII/RMII interface transmit enable inputTX_CTL: RGMII interface transmit control outputTX_ERA3A10 F14N14 P6 OMII/RMII interface transmit coding error outputTXD0A2B9E13M13 P7 OMII/RMII/RGMII interface transmit data output, bit 0 TXD1B1A9E14M14 N7 OMII/RMII/RGMII interface transmit data output, bit 1 TXD2C2B8D13L13P8 OMII/RGMII interface transmit data output, bit 2 TXD3C1A8D14L14N8 OMII/RGMII interface transmit data output, bit 3RX_CLK/RXCE2B6B14J13P10 I/OIRX_CLK: MII interface receive clock (also configurable as output)RXC.

8 RGMII interface receive clockRX_ERH2B3B10F13P13 IMII/RMII interface receive error inputRX_DV/ CRS_DV/RX_CTLG1A4A11G14 N12 IRX_DV: MII interface receive data valid inputCRS_DV: RMII interface carrier sense/data valid inputRX_CTL: RGMII interface receive control inputRXD0E1A6A13J14N10 IMII/RMII/RGMII interface receive data input, bit 0 RXD1F2B5B12H13 P11 IMII/RMII/RGMII interface receive data input, bit 1 RXD2F1A5A12H14 N11 IMII/RGMII interface receive data input, bit 2 RXD3G2B4B11G13 P12 IMII/RGMII interface receive data input, bit 3 Table description - core supply and groundSymbolPinType[1]DescriptionVDD_COR ED6, D9, F4, F11, J4, J11, L6, V core supply voltageVSSA1, A14, B13, E5, E6, E7, E8, E9, E10, F5, F6, F7, F8, F9, F10, G5, G6, G7, G8, G9, G10, H5, H6, H7, H8, H9, H10, J5, J6, J7, J8, J9, J10, K4, K5, K6, K7, K8, K9, K10, L7, N2, N13, P1, P14 Gsupply groundSJA1105 All information provided in this document is subject to legal disclaimers.

9 NXP Semiconductors 2016. All rights data sheetRev. 1 7 November 2016 7 of 34 NXP SemiconductorsSJA11055-port automotive ethernet switch [1]I: digital input; O: digital output; P: power supply, G: ground.[2]Pins RST_N and TRST_N must be held LOW simultaneously to reset the device.[3]JTAG pins have internal description - generalSymbolPinType[1]DescriptionRST_N[ 2]P3 Ireset input (active LOW)PTP_CLKN4 OPTP clockVDDIO_HOSTL5 Phost interface supply connected; must be connected to groundClock generation (CGU)VDDA_OSCK1 Poscillator supply voltageVSSA_OSCL2 Goscillator supply groundVDDA_PLLJ1 PPLL supply voltageVSSA_PLLJ2 GPLL supply groundVDDIO_CLOH4 Pclock output supply voltage (CLK_OUT)CLK_OUTH1 Oclock outputOSC_INK2 Ioscillator inputOSC_OUTL1 Ooscillator outputSPI interfaceSCKP5 ISPI clockSDIN5 ISPI data inputSDOP4 OSPI data outputSS_NN6 ISPI slave select (active LOW)JTAG interface[3]TRST_NM1 Itest reset (active LOW)TDIM2 Itest data inTCKN1 Itest clockTMSP2 Itest mode stateTDON3 Otest data outSJA1105 All information provided in this document is subject to legal disclaimers.

10 NXP Semiconductors 2016. All rights data sheetRev. 1 7 November 2016 8 of 34 NXP SemiconductorsSJA11055-port automotive ethernet switch6. Functional descriptionThe SJA1105 is designed to provide a cost-optimized and flexible solution for automotive ethernet switches. Each port can be independently configured for MII, RMII or RGMII operation. Switch configuration is performed via an SPI interface. A typical system diagram is shown in Figure 5. Functional overviewThe SJA1105 contains the following functional modules (see the block diagrams in Figure 1 and Figure 2) Auxiliary Configuration Unit (ACU)This module contains the pin configuration and status registers. The host can configure the I/O pads of the chip (pull-up/-down, speed etc.) and monitor the product configuration and temperature sensor status via these Clock Generation Unit (CGU)This module contains the oscillator and PLLs used to generate clocks for all internal blocks and a number of interface output Reset Generation Unit (RGU)This block ensures that the device transitions to a pre-defined state after power-up or an externally asserted diagram showing the SJA1105 ethernet switch connected to PHYs and a host processor6-$ 3257(7+(51(76:,7&+DDD 3+<3+<3+<63,60,[0,,[0,,[0,,[0,,3+<[0,,+2 67352&(6625 SJA1105 All information provided in this document is subject to legal disclaimers.))))]]]]]


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