16-Kbit serial I2C bus EEPROM - STMicroelectronics

1 TSSOP8 (DW)169 mil widthSO8 (MN)150 mil widthUFDFPN8 (MC)DFN8 - 2x3 mmUFDFPN5 (MH)DFN5 - mmUnsawn waferFeatures Compatible with following I2C bus modes: 400 kHz 100 kHz Memory array: 16 Kbit (2 Kbyte) of EEPROM Page size: 16 byte Single supply voltage: M24C16-W: V to V M24C16-R: V to V M24C16-F: V to V (full temperature range) and V to V(limited temperature range) Write time: Byte write within 5 ms Page write within 5 ms Operating temperature range: from -40 C up to +85 C Random and sequential read modes Write protect of the whole memory array Enhanced ESD/latch-up protection More than 4 million Write cycles More than 200-year data retentionPackages SO8 ECOPACK2 TSSOP8 ECOPACK2 UFDFPN8 ECOPACK2 UFDFPN5 ECOPACK2 Unsawn wafer (each die is tested)Product status linkM24C16-WM24C16-RM24C16-F16-Kbit serial I2C bus EEPROMM24C16-W M24C16-R M24C16-FDatasheetDS9194 - Rev 11 - October 2020 For further information contact your local STMicroelectronics sales M24C16 is a 16-Kbit I2C-compatible EEPROM (electrically erasable programmable memory) organized as2K x 8 M24C16-W can be accessed (Read and Write)

2 With a supply voltage from V to V, the M24C16-R canbe accessed (Read and Write) with a supply voltage from V to V, and the M24C16-F can be accessed witha supply voltage from V to V (over the full temperature range) or with an extended supply voltage V to V. The M24C16-F can also operate down to V, under some restricting these devices operate with a clock frequency of 400 kHz (or lower).Figure 1. Logic diagramMS30935V2 SDAM24xxxSCLWCVCCVSST able 1. Signal namesSignal nameFunctionDirectionSDAS erial dataI/OSCLS erial clockInputWCWrite controlInputVCCS upply voltage-VSSG round-Figure 2. 8-pin package connections, top viewMS30936V2 SDAVSSSCLNCNCNC12348765 VCCWC1. NC: Not ConnectedM24C16-W M24C16-R M24C16-FDescriptionDS9194 - Rev 11page 2/40 Figure 3.

3 UFDFPN5 (DFN5) package connectionsSDASCLWC1234 VCCVSS52123452 Top view(marking side)Bottom view(pads side)ABCDXYZWVSS1. See Section 9 Package information for package dimensions, and how to identify pin 1M24C16-W M24C16-R M24C16-FDescriptionDS9194 - Rev 11page 3/402 Signal clock (SCL)The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data onSDA(out). data (SDA)SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output thatmay be wire-OR'ed with other open drain or open collector signals on the bus. A pull-up resistor must beconnected from serial data (SDA) to VCC (Figure 11 indicates how to calculate the value of the pull-up resistor).

4 Control (WC)This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Writeoperations are disabled to the entire memory array when write control (WC) is driven high. Write operations areenabled when write control (WC) is either driven low or left write control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are (ground)VSS is the reference for the VCC supply voltage (VCC) supply voltage (VCC)Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified[VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8 DC and AC parameters).

5 Inorder to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor(usually of the order of 10 nF to 100 nF) close to the VCC/VSS package voltage must remain stable and valid until the end of the transmission of the instruction and, for a writeinstruction, until the completion of the internal write cycle (tW). conditionsThe VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operatingconditions in Section 8 DC and AC parameters). resetIn order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is power-up, the device does not respond to any instruction until VCC has reached the internal reset thresholdvoltage.

6 This threshold is lower than the minimum VCC operating voltage (see Operating conditions inSection 8 DC and AC parameters). When VCC passes over the POR threshold, the device is reset and entersthe Standby Power mode; the device must not be accessed until VCC reaches a valid and stable DC voltagewithin the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8 DC and AC parameters).In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCCdrops below VCC(min). When VCC drops below the threshold voltage, the device stops responding to anyinstruction sent to conditionsDuring power-down (continuous decrease in VCC), the device must be in the standby power mode (mode reachedafter decoding a Stop condition, assuming that there is no internal write cycle in progress).

7 M24C16-W M24C16-R M24C16-FSignal descriptionDS9194 - Rev 11page 4/403 Memory organizationThe memory is organized as shown 4. Block diagramHV GENERATOR +SEQUENCERI/O ARRAYSENSE AMPLIFIERSY DECODERDATA REGISTERCONTROLLOGICSCLSDAPAGE LATCHESX DECODERSTART & STOPDETECTADDRESSREGISTERWCM24C16-W M24C16-R M24C16-FMemory organizationDS9194 - Rev 11page 5/404 Device operationThe device supports the I2C protocol (see Figure 5). Any device that sends data on to the bus is defined atransmitter, and any device that reads the data a receiver. The device that controls the data transfer is known asthe bus master, and the other as the slave device.

8 A data transfer can only be initiated by the bus master, whichalso provides the serial clock for synchronization. The device is always a slave in all 5. I2C bus protocolSCLSDASCLSDASDASTARTC onditionSDAI nputSDAC hangeSTOP Condition123789 MSBACKSTARTC onditionSCL123789 MSBACKSTOP conditionStart is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A startcondition must precede any data transfer instruction. The device continuously monitors (except during a writecycle) serial data (SDA) and serial clock (SCL) for a start conditionStop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable and driven high.

9 A stopcondition terminates communication between the device and the bus master. A Read instruction that is followedby NoAck can be followed by a stop condition to force the device into the standby stop condition at the end of a Write instruction triggers the internal write inputDuring data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correctdevice operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data(SDA) signal must change only when serial clock (SCL) is driven M24C16-R M24C16-FDevice operationDS9194 - Rev 11page 6 bit (ACK)The acknowledge bit is used to indicate a successful byte transfer.

10 The bus transmitter, whether it be bus masteror slave device, releases serial data (SDA) after sending eight bits of data. During the ninth clock pulse period,the receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data addressingTo start communication between the bus master and the slave device, the bus master must initiate a Startcondition. Following this, the bus master sends the device select code, shown in not Table 2 (most significant bitfirst).Table 2. Device select codeDevice type identifier(1)Chip enable addressRWb7b6b5b4b3b2b1b01010A10A9A8RW 1. The most significant bit, b7, is sent first. The eighth bit is the Read/Write bit (R/W), set to 1 / 0, respectively, for Read / Write a match occurs on the device select code, the corresponding device gives an acknowledgement on serial data(SDA) during the ninth bit time.