2-Mbit serial I²C bus EEPROM - STMicroelectronics

1 This is information on a product in full production. January 2018 DocID18204 Rev 101/40M24M02-DR M24M02-R2- mbit serial i C bus EEPROM Datasheet - production dataFeatures Compatible with all I2C bus modes: 1 MHz 400 kHz 100 kHz Memory array: 2 Mbit (256 Kbyte) of EEPROM Page size: 256 byte Additional Write lockable page (M24M02-DR order codes) Single supply voltage: V to V over 40 C / +85 C Write: Byte Write within 10 ms Page Write within 10 ms Random and sequential Read modes Write protect of the whole memory array Enhanced ESD/Latch-Up protection More than 4 million Write cycles More than 200-years data retentionPackages SO8 ECOPACK2 WLCSP ECOPACK2 Unsawn wafer (each die is tested) RoHS compliant and halogen-free (ECOPACK2 )SO8 (MN)150 mil widthWLCSPU nsawn M24M02-R2/40 DocID18204 Rev 10 Contents1 Description .. 62 Signal description .. Clock (SCL) .. Data (SDA) .. Enable (E2).

2 Control (WC) .. (ground) .. voltage (VCC) .. supply voltage (VCC) .. conditions .. reset .. conditions .. 93 Memory organization .. 104 Device operation .. condition .. condition .. input .. bit (ACK) .. addressing .. 135 Instructions .. operations .. Write .. Write .. Identification Page (M24M02-DR only) .. Identification Page (M24M02-DR only) .. (Error Correction Code) and Write cycling .. Write delays by polling on ACK .. operations .. Address Read .. 20 DocID18204 Rev 103/40M24M02-DR Address Read .. Read .. Identification Page (M24M02-DR only) .. the lock status (M24M02-DR only) .. 216 Initial delivery state .. 227 Maximum rating .. 238DC and AC parameters .. 249 Package information .. package information .. package information .. 3310 Ordering information .. 3511 Revision history .. 38 List of tablesM24M02-DR M24M02-R4/40 DocID18204 Rev 10 List of tablesTable names.

3 6 Table vs. bump position .. 7 Table select code .. 13 Table significant address byte .. 14 Table significant address byte .. 14 Table maximum ratings .. 23 Table conditions .. 24 Table measurement conditions.. 24 Table parameters.. 24 Table performance .. 25 Table cell data retention .. 25 Table characteristics.. 26 Table kHz AC characteristics.. 27 Table MHz AC characteristics .. 28 Table mm, 8-lead plastic small outline, 150 mils body width, package mechanical data .. 32 Table 8-bump, x mm, wafer level chip scale package mechanical data .. 34 Table information scheme .. 35 Table information scheme (unsawn wafer) .. 36 Table revision history .. 38 DocID18204 Rev 105/40M24M02-DR M24M02-RList of figures5 List of figuresFigure diagram .. 6 Figure connections, top view .. 6 Figure 3. WLCSP connections .. 7 Figure enable inputs connection .. 8 Figure diagram .. 10 Figure bus protocol.

4 11 Figure mode sequences with WC = 0 (data write enabled) .. 15 Figure mode sequences with WC = 1 (data write inhibited) .. 16 Figure cycle polling flowchart using ACK .. 18 Figure mode sequences .. 19 Figure measurement I/O waveform .. 24 Figure Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz.. 29 Figure Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1 MHz .. 29 Figure waveforms .. 30 Figure mm, 8-lead plastic small outline, 150 mils body width, package outline . 32 Figure mm, 8-lead plastic small outline, 150 mils body width, package recommended footprint .. 33 Figure 8-bump, x mm, wafer level chip scale package outline.. 33 Figure 8-bump, x mm, wafer level chip scale package recommended footprint .. 34 DescriptionM24M02-DR M24M02-R6/40 DocID18204 Rev 101 DescriptionThe M24M02 is a 2 Mbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 256 K 8 M24M02-DR and M24M02-R can operate with a supply voltage from V to V, over an ambient temperature range of 40 C / +85 C.

5 The M24M02-DR offers an additional page, named the Identification Page (256 byte). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only 1. Logic diagram Figure 2. SO8 connections, top view1. DU: Don t use (no signal should be applied on this pin; if connected, must be connected to VSS)2. See Section 9: Package information for package dimensions, and how to identify pin 1 Table 1. Signal namesSignal nameFunctionDirectionE2 Chip EnableInputSDAS erial DataI/OSCLS erial ClockInputWCWrite ControlInputVCCS upply voltage-VSSG round-06 9 6'$9&&0 0 [5:&6&/966( 3$!6333#,7#$5$56##% !) V DocID18204 Rev 107/40M24M02-DR M24M02-RDescription39 Figure 3. WLCSP connections1. DU: Don t use (no signal should be applied on this pin; if connected, must be connected to Vss)2. See Section 9: Package information for package dimensions, and how to identify pin 1.]

6 Table 2. Signals vs. bump positionPositionABCD1-- SCL -2 VCCWC-SDA3DU-- VSS4- DU E2 -06 9 0 DUNLQJ VLGH WRS YLHZ $%&'%XPS VLGH ERWWRP YLHZ $%&'Signal descriptionM24M02-DR M24M02-R8/40 DocID18204 Rev 102 Signal serial Clock (SCL)The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). serial Data (SDA)SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected (Figure 12 indicates how to calculate the value of the pull-up resistor). Chip Enable (E2)This input signal is used to set the value that is to be looked for on the bit b3 of the 7-bit device select code. This input must be tied to VCC or VSS, to establish the device select code as shown in Figure 4.

7 When not connected (left floating), this input is read as low (0 Figure 4. Chip enable inputs Write Control (WC)This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not VSS (ground)VSS is the reference for the VCC supply voltage.$L 9&&0 [[[966(L9&&0 [[[966(LDocID18204 Rev 109/40M24M02-DR M24M02-RSignal Supply voltage (VCC) Operating supply voltage (VCC)Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters).)))]]]]]]

8 In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). Power-up conditionsThe VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). Device resetIn order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters).

9 In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to Power-down conditionsDuring power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress).Memory organizationM24M02-DR M24M02-R10/40 DocID18204 Rev 103 Memory organizationThe memory is organized as shown 5. Block diagram-3 6 7##ONTROL LOGIC(IGH VOLTAGEGENERATOR) / SHIFT REGISTER!DDRESS REGISTERAND COUNTER$ATAREGISTER PAGE8 DECODER9 DECODER)DENTIFICATION PAGE% 3#,3$!DocID18204 Rev 1011/40M24M02-DR M24M02-RDevice operation394 Device operationThe device supports the I2C protocol. This is summarized in Figure 6.

10 Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all 6. I2C bus protocolDevice operationM24M02-DR M24M02-R12/40 DocID18204 Rev Start conditionStart is identified by a falling edge of serial Data (SDA) while serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) serial Data (SDA) and serial Clock (SCL) for a Start Stop conditionStop is identified by a rising edge of serial Data (SDA) while serial Clock (SCL) is stable and driven high.