24AA64 Data Sheet - Microchip Technology

1 1997-2012 Microchip Technology 124AA64/24LC64/24FC64 Device Selection TableFeatures: Single-Supply with Operation down to for 24AA64 /24FC64 Devices, for 24LC64 Devices Low-Power CMOS Technology :- Active current 3 mA, Standby current 1 A, max. 2-Wire Serial Interface, I2C Compatible Packages with 3 Address Pins are Cascadable up to 8 Devices Schmitt Trigger Inputs for Noise Suppression Output Slope Control to Eliminate Ground Bounce 100 kHz and 400 kHz Clock Compatibility 1 MHz Clock for FC versions Page Write Time 5 ms, max. Self-timed Erase/Write Cycle 32-Byte Page Write Buffer Hardware Write-Protect ESD Protection > 4,000V More than 1 Million Erase/Write Cycles Data Retention > 200 Years Factory Programming Available Packages include 8-lead PDIP, SOIC, SOIJ, TSSOP, X-Rotated TSSOP, MSOP, DFN, TDFN, 5-lead SOT-23 or Chip Scale Pb-Free and RoHS Compliant Temperature Ranges:- Industrial (I): -40 C to +85 C- Automotive (E): -40 C to +125 CDescription:The Microchip Technology Inc.

2 24AA64 /24LC64/24FC64 (24XX64*) is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to , with standby and active currents of only 1 A and 3 mA, respectively. It has been developed for advanced, low-power applications such as personal communications or data acquisition. The 24XX64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space . The 24XX64 is available in the standard 8-pin PDIP, surface mount SOIC, SOIJ, TSSOP, DFN, TDFN and MSOP packages.

3 The 24XX64 is also available in the 5-lead SOT-23, and Chip Scale DiagramPackage TypesPart NumberVCC RangeMax. Clock FrequencyTemp. kHz(1)I, kHzI, MHz(2)INote 1:100 kHz for VCC < :400 kHz for VCC < EEPROM ArrayPage YDECXDECS ense ControlLatchesGeneratorA2A1A0A0A1A2 VSSVCCWPSCLSDA12348765 PDIP/MSOP/SOIC/SOIJ/TSSOPDFN/TDFNA0A1A2 VSSWPSCLSDAVCC87651234 SOT-2312345 WPVCCSCLVSSSDACS (Chip Scale)(1)12345 VCCWPSDASCLVSS(Top Down View,Balls Not Visible)Note 1:Available in I-temp, AA TSSOPWPVCCA0A112348765 SCLSDAVSSA2(X/ST)64K I2C Serial EEPROM* 24XX64 is used in this document as a generic part number for the 24AA64 /24LC64/24FC64 2 1997-2012 Microchip Technology CHARACTERISTICSA bsolute Maximum Ratings ( ) inputs and outputs to VCC + temperature.

4 -65 C to +150 CAmbient temperature with power applied ..-40 C to +125 CESD protection on all pins 4kVTABLE 1-1:DC CHARACTERISTICS NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions forextended periods may affect device CHARACTERISTICSI ndustrial (I): TA = -40 C to +85 C, VCC = + to + (E).

5 TA = -40 C to +125 C, VCC = + to + A0, A1, A2, WP, SCL and SDA pins D1 VIHHigh-level input VCC V D2 VILLow-level input voltage VCCVVVCC of SchmittTrigger inputs (SDA, SCL pins) VCC VVCC (Note 1)D4 VOLLow-level output voltage = mA @ VCC = = mA @ VCC = leakage current 1 AVIN = VSS or VCC, WP = VSSVIN = VSS or VCC, WP = VCCD6 ILOO utput leakage current 1 AVOUT = VSS or VCCD7 CIN, COUTPin capacitance(all inputs/outputs) 10pFVCC = (Note 1)TA = 25 C, FCLK = 1 MHzD8 ICC writeOperating current 3mAVCC = , SCL = 400 kHzD9 ICC read AD10 ICCSS tandby current 15 A AIndustrialAutomotiveSDA = SCL = VCCA0, A1, A2, WP = VSSNote 1:This parameter is periodically sampled and not 100% :Typical measurements taken at room temperature.

6 1997-2012 Microchip Technology 324AA64/24LC64/24FC64 TABLE 1-2:AC CHARACTERISTICSAC CHARACTERISTICSE lectrical Characteristics:Industrial (I):VCC = + to TA = -40 C to +85 CAutomotive (E):VCC = + to TA = -40 C to 125 frequency VCC VCC VCC VCC 24FC642 THIGHC lock high time4000600600500 VCC VCC VCC VCC 24FC643 TLOWC lock low time470013001300500 VCC VCC VCC VCC 24FC644 TRSDA and SCL rise time(Note 1) VCC VCC VCC 24FC645 TFSDA and SCL fall time(Note 1) 300100nsAll except, VCC 24FC646 THD:STAS tart condition hold time4000600600250 VCC VCC VCC VCC 24FC647 TSU.

7 STAS tart condition setup time4700600600250 VCC VCC VCC VCC 24FC648 THD:DATData input hold time0 ns(Note 2)9 TSU:DATData input setup time250100100 VCC VCC VCC 24FC6410 TSU:STOStop condition setup time4000600600250 V VCC V VCC VCC V VCC 24FC6411 TSU:WPWP setup time4000600600 VCC VCC VCC 24FC6412 THD:WPWP hold time470013001300 VCC VCC VCC 24FC64 Note 1:Not 100% tested. CB = total capacitance of one bus line in :As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop :The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improvednoise spike suppression.

8 This eliminates the need for a TI specification for standard :This parameter is not tested but ensured by characterization. For endurance estimates in a specificapplication, please consult the Total Endurance Model, which can be obtained from Microchip s web siteat 4 1997-2012 Microchip Technology 1-1:BUS TIMING DATA 13 TAAO utput valid from clock(Note 2) VCC VCC VCC VCC 24FC6414 TBUFBus free time: Time the bus must be free before a new transmission can start470013001300500 VCC VCC VCC VCC 24FC6415 TOFO utput fall time from VIHminimum to VIL maximumCB 100 pF10 + except, 24FC64 (Note 1)24FC64 (Note 1)16 TSPI nput filter spike suppression(SDA and SCL pins) 50nsAll except, 24FC64 (Notes 1 and3)17 TWCW rite cycle time (byte or page) 5ms 18 Endurance1,000,000 cycles Page Mode 25 C, (Note 4)AC CHARACTERISTICSE lectrical Characteristics:Industrial (I):VCC = + to TA = -40 C to +85 CAutomotive (E).

9 VCC = + to TA = -40 C to 125 1:Not 100% tested. CB = total capacitance of one bus line in :As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop :The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improvednoise spike suppression. This eliminates the need for a TI specification for standard :This parameter is not tested but ensured by characterization. For endurance estimates in a specificapplication, please consult the Total Endurance Model, which can be obtained from Microchip s web siteat (unprotected)(protected)SCLSDAINSDAOUTWP 57616328913D3410111214 1997-2012 Microchip Technology 524AA64/24LC64 DESCRIPTIONSThe descriptions of the pins are listed in Ta b l e 2 - 2-1:PIN FUNCTION , A1, A2 Chip Address InputsThe A0, A1 and A2 inputs are used by the 24XX64 formultiple device operation.

10 The levels on these inputsare compared with the corresponding bits in the slaveaddress. The chip is selected if the compare is to eight devices may be connected to the same busby using different Chip Select bit combinations. Theseinputs must be connected to either VCC or VSS. In most applications, the chip address inputs A0, A1and A2 are hard-wired to logic 0 or logic 1 . Forapplications in which these pins are controlled by amicrocontroller or other programmable device, the chipaddress pins must be driven to logic 0 or logic 1 before normal device operation can proceed.