SST25VF016B - Microchip Technology

1 2015 Microchip Technology Inc. DS20005044C-page 1 Features Single Voltage Read and Write Operations- Serial Interface Architecture- SPI Compatible: Mode 0 and Mode 3 High Speed Clock Frequency- Up to 50 MHz Superior Reliability- Endurance: 100,000 Cycles (typical)- Greater than 100 years Data Retention Low Power Consumption:- Active Read Current: 10 mA (typical)- Standby Current: 5 A (typical) Flexible Erase Capability- Uniform 4 KByte sectors- Uniform 32 KByte overlay blocks- Uniform 64 KByte overlay blocks Fast Erase and Byte-Program:- Chip-Erase Time: 35 ms (typical)- Sector-/Block-Erase Time: 18 ms (typical)- Byte-Program Time: 7 s (typical) Auto Address Increment (AAI) Programming- Decrease total chip programming time over Byte-Program operations End-of-Write Detection- Software polling the BUSY bit in Status Register- Busy Status readout on SO pin in AAI Mode Hold Pin (HOLD#)- Suspends a serial sequence to the memorywithout deselecting the device Write Protection (WP#)- Enables/Disables the Lock-Down function of the status register Software Write Protection- Write protection through Block-Protection bits in status register Temperature Range- Commercial: 0 C to +70 C- Industrial: -40 C to +85 C Packages Available- 8-lead SOIC (200 mils)- 8-contact WSON (6mm x 5mm) All devices are RoHS compliantProduct DescriptionThe 25 series Serial Flash family features a four-wire,SPI-compatible interface that allows for a low pin-countpackage which occupies less board space and ulti-mately lowers total system costs.

2 The SST25VF016 Bdevices are enhanced with improved operating fre-quency and even lower power consumption than theoriginal SST25 VFxxxA devices. SST25VF016B SPIserial flash memories are manufactured with propri-etary, high-performance CMOS SuperFlash technol-ogy. The split-gate cell design and thick-oxide tunnelinginjector attain better reliability and manufacturabilitycompared with alternate devices significantly improve perfor-mance and reliability, while lowering power consump-tion. The devices write (Program or Erase) with a singlepower supply of for SST25VF016B . The totalenergy consumed is a function of the applied voltage,current, and time of application. Since for any givenvoltage range, the SuperFlash Technology uses lesscurrent to program and has a shorter erase time, thetotal energy consumed during any Erase or Programoperation is less than alternative flash memory technol-ogies.

3 The SST25VF016B device is offered in both 8-leadSOIC (200 mils) and 8-contact WSON (6mm x 5mm)packages. See Figure 2-1 for pin Mbit SPI Serial FlashSST25VF016 BDS20005044C-page 2 2015 Microchip Technology OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at We welcome your Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

4 Thelast character of the literature number is the version number, ( , DS30000000A is version A of document DS30000000).ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision ofsilicon and revision of document to which it determine if an errata sheet exists for a particular device, please check with one of the following: Microchip s Worldwide Web site; Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you Notification SystemRegister on our web site at to receive the most current information on all of our products. 2015 Microchip Technology Inc. DS20005044C-page DIAGRAMFIGURE 1-1:FUNCTIONAL BLOCK DIAGRAM1271 BuffersandData LatchesSuperFlashMemoryX - DecoderControl LogicAddressBuffersandLatchesCE#Y - DecoderSCKSISO WP#HOLD#Serial InterfaceSST25VF016 BDS20005044C-page 4 2015 Microchip Technology DESCRIPTIONFIGURE 2-1:PIN ASSIGNMENTSTABLE 2-1:PIN DESCRIPTIONS ymbol Pin NameFunctionsSCKS erial ClockTo provide the timing of the serial , addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock Data InputTo transfer commands, addresses, or data serially into the are latched on the rising edge of the serial Data OutputTo transfer data serially out of the is shifted out on the falling edge of the serial Flash busy status during AAI Programming when reconfigured as RY/BY# pin.

5 See Hardware End-of-Write Detection on page 11 for #Chip EnableThe device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command #Write ProtectThe Write Protect (WP#) pin is used to enable/disable BPL bit in the status #HoldTo temporarily stop serial communication with SPI flash memory without resetting the SupplyTo provide power supply voltage: for SST25VF016 BVSSG round12348765CE#SOWP#VSSVDD HOLD#SCKSITop View1271 08-soic S2A #SOWP#VSSTop ViewVDDHOLD#SCKSI1271 08-wson QA SOIC8-Contact WSON 2015 Microchip Technology Inc. DS20005044C-page ORGANIZATIONThe SST25VF016B SuperFlash memory array is orga-nized in uniform 4 KByte erasable sectors with32 KByte overlay blocks and 64 KByte overlay eras-able OPERATIONThe SST25VF016B is accessed through the SPI (SerialPeripheral Interface) bus compatible protocol. The SPIbus consist of four control lines; Chip Enable (CE#) isused to select the device, and data is accessed throughthe Serial Data Input (SI), Serial Data Output (SO), andSerial Clock (SCK).

6 The SST25VF016B supports both Mode 0 (0,0) andMode 3 (1,1) of SPI bus operations. The differencebetween the two modes, as shown in Figure 4-1, is thestate of the SCK signal when the bus master is inStand-by mode and no data is being transferred. TheSCK signal is low for Mode 0 and SCK signal is high forMode 3. For both modes, the Serial Data In (SI) is sam-pled at the rising edge of the SCK clock signal and theSerial Data Output (SO) is driven after the falling edgeof the SCK clock 4-1:SPI OperationThe HOLD# pin is used to pause a serial sequenceunderway with the SPI flash memory without resettingthe clocking sequence. To activate the HOLD# mode,CE# must be in active low state. The HOLD# modebegins when the SCK active low state coincides withthe falling edge of the HOLD# signal. The HOLD modeends when the HOLD# signal s rising edge coincideswith the SCK active low the falling edge of the HOLD# signal does not coin-cide with the SCK active low state, then the deviceenters Hold mode when the SCK next reaches theactive low state.

7 Similarly, if the rising edge of theHOLD# signal does not coincide with the SCK activelow state, then the device exits in Hold mode when theSCK next reaches the active low state. See Figure 4-2for Hold Condition the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or CE# is driven active high during a Hold condition, itresets the internal logic of the device. As long asHOLD# signal is low, the memory remains in the Holdcondition. To resume communication with the device,HOLD# must be driven active high, and CE# must bedriven active low. See Figure 5-3 for Hold 4-2:HOLD CONDITION ProtectionSST25VF016B provides software Write protection. TheWrite Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protec-tion bits (BP3, BP2, BP1, BP0, and BPL) in the statusregister provide Write protection to the memory arrayand the status register.

8 See Table 4-3 for the Block-Pro-tection 3 SCKSISOCE#MODE 3 DON'T CAREBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MODE 0 MODE 0 HIGH IMPEDANCEMSBMSBA ctiveHoldActiveHoldActive1271 #SST25VF016 BDS20005044C-page 6 2015 Microchip Technology PROTECT PIN (WP#)The Write Protect (WP#) pin enables the lock-downfunction of the BPL bit (bit 7) in the status WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined bythe value of the BPL bit (see Table 4-1). When WP# ishigh, the lock-down function of the BPL bit is RegisterThe software status register provides status onwhether the flash memory array is available for anyRead or Write operation, whether the device is Writeenabled, and the state of the Memory Write an internal Erase or Program operation, the sta-tus register may be read only to determine the comple-tion of an operation in progress.

9 Table 4-2 describesthe function of each bit in the software status Busy bit determines whether there is an internalErase or Program operation in progress. A 1 for theBusy bit indicates the device is busy with an operationin progress. A 0 indicates the device is ready for thenext valid ENABLE LATCH (WEL)The Write-Enable-Latch (WEL) bit indicates the statusof the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to 1 , it indicates the device isWrite enabled. If the bit is set to 0 (reset), it indicatesthe device is not Write enabled and does not acceptany memory Write (Program/Erase) commands. TheWrite-Enable-Latch bit is automatically reset under thefollowing conditions: Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming is completed or reached its highest unprotected memory address Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion Write-Status-Register ADDRESS INCREMENT (AAI)The Auto Address Increment Programming-Status bitprovides status on whether the device is in AutoAddress Increment (AAI) programming mode or Byte-Program mode.

10 The default at power up is Byte-Pro-gram 4-1:CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTIONWP#BPLE xecute WRSR InstructionL1 Not AllowedL0 AllowedHXAllowedTABLE 4-2:SOFTWARE STATUS REGISTERBitNameFunctionDefault atPower-upRead/Write0 BUSY1 = Internal Write operation is in progress0 = No internal Write operation is in progress0R1 WEL1 = Device is memory Write enabled0 = Device is not memory Write enabled0R2BP0 Indicate current level of block write protection (See Table 4-3)1R/W3BP1 Indicate current level of block write protection (See Table 4-3)1R/W4BP2 Indicate current level of block write protection (See Table 4-3)1R/W5BP3 Indicate current level of block write protection (See Table 4-3)0R/W6 AAIAuto Address Increment Programming status1 = AAI programming mode0 = Byte-Program mode0R7 BPL1 = BP3, BP2, BP1, BP0 are read-only bits0 = BP3, BP2, BP1, BP0 are read/writable0R/W 2015 Microchip Technology Inc. DS20005044C-page PROTECTION (BP3,BP2, BP1, BP0)The Block-Protection (BP3, BP2, BP1, BP0) bits definethe size of the memory area, as defined in Table 4-3, tobe software protected against any memory Write (Pro-gram or Erase) operation.