24LC16B 16K I2C Serial EEPROM High Temp Data Sheet

1 24LC16B . 16K I2C Serial EEPROM High Temp Data Sheet Device Selection Table Part Number VCC Range Max. Clock Frequency Temp. Ranges Packages 24LC16B 400 kHz H SN, OT. Features Description Single Supply with Operation down to The Microchip Technology Inc. 24LC16B is a 16 Kbit Low-Power CMOS Technology: Electrically Erasable PROM. The device is organized - Active current, 1 mA, typical as eight blocks of 256 x 8-bit memory with a 2-wire Serial interface. Low-voltage design permits operation - Standby current, 1 A, typical down to with standby and active currents of only 2-Wire Serial Interface, I2C Compatible 1 A and 1 mA, respectively. The 24LC16B also has a Schmitt Trigger inputs for Noise Suppression page write capability for up to 16 bytes of data. The Output Slope Control to Eliminate Ground Bounce 24LC16B is available in the standard 8-pin surface 100 kHz and 400 kHz Clock Compatibility mount SOIC and in the 5-lead SOT-23 packages.

2 Page Write Time 5 ms Maximum Block Diagram Self-Timed Erase/Write Cycle HV. 16-Byte Page Write Buffer WP Generator Hardware Write-Protect ESD Protection > 4,000V. More than 1 Million Erase/Write Cycles I/O Memory EEPROM . Control Control XDEC Array Data Retention > 200 Years Logic Logic Factory Programming Available Page Packages include 8-lead SOIC and 5-lead SOT-23 Latches RoHS Compliant I/O. SCL. YDEC. Temperature Ranges: - Extended (H): -40 C to +150 C SDA. VCC. VSS Sense Amp. R/W Control Package Types (not to scale). SOIC SOT-23. A0 1 8 VCC SCL 1 5 WP. A1 2 7 WP VSS 2. A2 3 6 SCL 3 4 VCC. SDA. VSS 4 5 SDA. Note 1: Pins A0, A1 and A2 are not used by the 24LC16B . (no internal connections). 2018 Microchip Technology Inc. DS20006054A-page 1. 24LC16B . ELECTRICAL CHARACTERISTICS. Absolute Maximum Ratings ( ). VCC .. All inputs and outputs VSS.

3 To VCC + Storage -65 C to +155 C. Ambient Temperature with Power -40 C to +150 C(1). ESD Protection on all Pins 4 kV. Note 1: AEC-Q100 reliability testing for devices intended to operate at 150 C is 1,000 hours. Any design in which the total operating time from 125 C to 150 C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS. DC CHARACTERISTICS Extended (H): TA = -40 C to +150 C, VCC = + to + Param.

4 Symbol Characteristic Min. Max. Units Conditions No. WP, SCL and SDA pins D1 VIH High-level input voltage VCC V . D2 VIL Low-level input voltage VCC V . D3 VHYS Hysteresis of Schmitt VCC V (Note 1). Trigger inputs D4 VOL Low-level output voltage V IOL = mA, VCC = D5 ILI Input leakage current 1 A VIN = VSS or VCC. D6 ILO Output leakage current 1 A VOUT = VSS or VCC. D7 CIN, Pin capacitance 10 pF VCC = (Note 1). COUT (all inputs/outputs) TA = 25 C, FCLK = 1 MHz D8 ICC write Operating current 3 mA VCC = , SCL = 400 kHz D9 ICC read 1 mA . D10 ICCS Standby current 1 A TA = -40 C to +85 C. 5 A TA = +85 C to +150 C. SDA = SCL = VCC. WP = VSS. Note 1: This parameter is periodically sampled and not 100% tested. DS20006054A-page 2 2018 Microchip Technology Inc. 24LC16B . TABLE 1-2: AC CHARACTERISTICS. AC CHARACTERISTICS Extended (H): TA = -40 C to +150 C, VCC = + to + Param.

5 Symbol Characteristic Min. Max. Units Conditions No. 1 FCLK Clock frequency 400 kHz . 2 THIGH Clock High Time 600 ns . 3 TLOW Clock Low Time 1300 ns . 4 TR SDA and SCL rise time 300 ns (Note 1). 5 TF SDA and SCL fall time 300 ns (Note 1). 6 THD:STA Start condition hold time 600 ns . 7 TSU:STA Start condition setup time 600 ns . 8 THD:DAT Data input hold time 0 ns (Note 2). 9 TSU:DAT Data input setup time 100 ns . 10 TSU:STO Stop condition setup time 600 ns . 11 TAA Output valid from clock 900 ns . (Note 2). 12 TBUF Bus free time: Time the bus 1300 ns . must be free before a new transmission can start 13 TOF Output fall time from VIH 20+ 250 ns . minimum to VIL maximum 14 TSP Input filter spike suppression 50 ns (Notes 1 and 3). (SDA and SCL pins). 15 TWC Write cycle time 5 ms . (byte or page). 16 Endurance 1M cycles Page mode, 25 C, (Note 4).

6 Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, consult the Total Endurance Model which can be obtained from Microchip's website at 2018 Microchip Technology Inc. DS20006054A-page 3. 24LC16B . FIGURE 1-1: BUS TIMING DATA. 5 4. 2. 3. SCL. 7 8 9 10. 6. SDA. IN 14. 11 12. SDA. OUT.

7 FIGURE 1-2: BUS TIMING START/STOP. D3. SCL. 6. 7 10. SDA. Start Stop DS20006054A-page 4 2018 Microchip Technology Inc. 24LC16B . PIN DESCRIPTIONS. The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE. Name SOIC SOT-23 Description A0 1 Not Connected A1 2 Not Connected A2 3 Not Connected VSS 4 2 Ground SDA 5 3 Serial Address/Data I/O. SCL 6 1 Serial Clock WP 7 5 Write-Protect Input VCC 8 4 + to Power Supply Serial Address/Data Input/Output Write-Protect (WP). (SDA) The WP pin must be connected to either VSS or VCC. The SDA is a bidirectional pin used to transfer If tied to VSS, normal memory operation is enabled addresses and data into and out of the device. Since it (read/write the entire memory 000-7FF). is an open-drain terminal, the SDA bus requires a pull- If tied to VCC, write operations are inhibited.

8 The entire up resistor to VCC (typical 10 k for 100 kHz, 2 k for memory will be write-protected. Read operations are 400 kHz). not affected. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are A0, A1, A2. reserved for indicating Start and Stop conditions. The A0, A1 and A2 pins are not used by the 24LC16B . Serial Clock (SCL) They may be left floating or tied to either VSS or VCC. The SCL input is used to synchronize the data transfer to and from the device. 2018 Microchip Technology Inc. DS20006054A-page 5. 24LC16B . FUNCTIONAL DESCRIPTION Data Valid (D). The 24LC16B supports a bidirectional, 2-wire bus and The state of the data line represents valid data when, data transmission protocol. A device that sends data after a Start condition, the data line is stable for the onto the bus is defined as a transmitter, while a device duration of the high period of the clock signal.

9 Receiving data is defined as a receiver. The bus has to The data on the line must be changed during the low be controlled by a master device which generates the period of the clock signal. There is one clock pulse per Serial Clock (SCL), controls the bus access and bit of data. generates the Start and Stop conditions, while the 24LC16B works as slave. Both master and slave can Each data transfer is initiated with a Start condition and operate as transmitter or receiver, but the master terminated with a Stop condition. The number of data device determines which mode is activated. bytes transferred between Start and Stop conditions is determined by the master device and is, theoretically, unlimited (although only the last sixteen will be stored BUS CHARACTERISTICS when doing a write operation). When an overwrite does occur it will replace data in a First-in First-out (FIFO).

10 The following bus protocol has been defined: fashion. Data transfer may be initiated only when the bus is not busy. Acknowledge During data transfer, the data line must remain stable whenever the clock line is high. Changes in Each receiving device, when addressed, is obliged to the data line while the clock line is high will be generate an Acknowledge after the reception of each interpreted as a Start or Stop condition. byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Accordingly, the following bus conditions have been defined (Figure 4-1). Note: The 24LC16B does not generate any Acknowledge bits if an internal Bus Not Busy (A) programming cycle is in progress. Both data and clock lines remain high. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable-low during the high Start Data Transfer (B).