24LC16B Data Sheet - Microchip Technology

1 2009-2016 Microchip Technology 124LC16 BDevice Selection TableFeatures Single Supply with Operation down to Low-Power CMOS Technology :- Active current 1 mA, typical- Standby current, 1 A, typical 2-Wire Serial Interface, I2C Compatible Schmitt Trigger Inputs for Noise Suppression Output Slope Control to Eliminate Ground Bounce 100 kHz and 400 kHz Clock Compatibility Page Write Time 5 ms Maximum Self-Timed Erase/Write Cycle 16-Byte Page Write Buffer Hardware Write-Protect ESD Protection >4,000V More than 1 Million Erase/Write Cycles Data Retention >200 Years Factory Programming Available RoHS Compliant Temperature Ranges:- Extended (M): -55 C to +125 CDescriptionThe Microchip Technology Inc. 24LC16B is a 16 KbitElectrically Erasable PROM. The device is organizedas eight blocks of 256 x 8-bit memory with a 2-wireserial interface. Low-voltage design permits operationdown to with standby and active currents of only1 A and 1 mA, respectively.

2 The 24LC16B also has apage write capability for up to 16 bytes of data. The24LC16B is available in the standard 8-pin SOIC and 5-lead SOT-23 TypesBlock DiagramPart NumberVCC RangeMax. Clock FrequencyTemp. kHzMSOICA0A1A2 VSS12348765 VCCWPSCLSDANote:Pins A0, A1 and A2 are not used by the24LC16B (no internal connections).SOT-23 SDAVSSVCC12354 WPSCLHV EEPROM ArrayPage YDECXDECS ense ControlLatchesGenerator16K I2C Serial EEPROM Extended (-55 C to +125 C) Operating Temperatures24LC16 BDS20002213B-page 2 2009-2016 Microchip Technology CHARACTERISTICSA bsolute Maximum Ratings ( ) inputs and outputs to VCC + temperature ..-65 C to +150 CAmbient temperature with power applied ..-55 C to +125 CESD protection on all pins 4kVTABLE 1-1:DC CHARACTERISTICS NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at those or any other conditions above thoseindicated in the operational listings of this specification is not implied.

3 Exposure to maximum rating conditions forextended periods may affect device CHARACTERISTICSE xtended (M): TA = -55 C to +125 C, VCC = + to + (2) Input VCC VD2 VILLow-Level Input Voltage VCCVD3 VHYSH ysteresis of SchmittTrigger VCC VNote 1D4 VOLLow-Level Output Voltage = mA, VCC= Leakage Current 1 AVIN=VSS or VCCD6 ILOO utput Leakage Current 1 AVOUT = VSS or VCCD7 CINPin Capacitance(all inputs/outputs) 10pFVCC = (Note 1)TA = 25 C, FCLK=1 MHzCOUTD8 ICCWRITE Operating current 3mAVCC = , SCL = 400 kHzD9 ICCREAD Current 1 A+85 C, SDA = SCL = VCCWP = VSS 5 A+125 C, SDA = SCL = VCCWP = VSSNote 1:This parameter is periodically sampled and not 100% :Typical measurements taken at room temperature. 2009-2016 Microchip Technology 324LC16 BTABLE 1-2:AC CHARACTERISTICSAC CHARACTERISTICSE xtended (M): TA = -55 C to +125 C, VCC = + to + Frequency 400kHz2 THIGHC lock High Time600 ns3 TLOWC lock Low Time1300 ns4 TRSDA and SCL Rise Time (Note 1) 300nsNote 15 TFSDA and SCL Fall Time 300nsNote 16 THD:STAS tart Condition Hold Time600 ns4000 ns7 TSU:STAS tart Condition Setup Time600 ns8 THD:DATData Input Hold Time0 nsNote 29 TSU:DATData Input Setup Time100 ns10 TSU:STOStop Condition Setup Time600 ns11 TAAO utput Valid from Clock (Note 2) 900ns12 TBUFBus Free Time: Bus time must be free before a new transmission can start1300 ns13 TOFO utput Fall Time from VIH Minimum to VIL Maximum20+ Filter Spike Suppression(SDA and SCL pins) 50nsNotes 1 and315 TWCW rite Cycle Time (byte or page) 5ms16 Endurance1M cycles Page mode, +25 C, (Note 4)Note 1:Not 100% tested.

4 CB = total capacitance of one bus line in :As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop :The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard :This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained from Microchip s website at 4 2009-2016 Microchip Technology 1-1:BUS TIMING DATAFIGURE 1-2:BUS TIMING START/STOP752489101211146 SCLSDAINSDAOUT376D310 StartStopSCLSDA 2009-2016 Microchip Technology DESCRIPTIONSThe descriptions of the pins are listed in Ta b l e 2 - 2-1:PIN FUNCTION Address/Data Input/Output (SDA)SDA is a bidirectional pin used to transfer addressesand data into and out of the device.

5 Since it is anopen-drain terminal, the SDA bus requires a pull-upresistor to VCC (typical 10 k for 100 kHz, 2 k for400 kHz).For normal data transfer, SDA is allowed to changeonly during SCL low. Changes during SCL high arereserved for indicating Start and Stop Clock (SCL)The SCL input is used to synchronize the data transferto and from the (WP) The WP pin must be connected to either VSS or tied to VSS, normal memory operation is enabled(read/write the entire memory 000-7FF).If tied to VCC, write operations are inhibited. The entirememory will be write-protected. Read operations arenot , A1, A2 The A0, A1 and A2 pins are not used by the may be left floating or tied to either VSS or SOIC5-pin SOT-23 DescriptionA01 Not ConnectedA12 Not ConnectedA23 Not ConnectedVSS42 GroundSDA53 Serial Address/Data I/OSCL61 Serial ClockWP75 Write-Protect InputVCC84+ to + Power Supply24LC16 BDS20002213B-page 6 2009-2016 Microchip Technology DESCRIPTIONThe 24LC16B supports a bidirectional, 2-wire bus anddata transmission protocol.

6 A device that sends dataonto the bus is defined as a transmitter, while a devicereceiving data is defined as a receiver. The bus has tobe controlled by a master device which generates theSerial Clock (SCL), controls the bus access andgenerates the Start and Stop conditions, while the24LC16B works as slave. Both master and slave canoperate as transmitter or receiver, but the masterdevice determines which mode is CHARACTERISTICSThe following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop , the following bus conditions have beendefined (Figure 4-1). Not Busy (A)Both data and clock lines remain Data Transfer (B)A high-to-low transition of the SDA line while the clock(SCL) is high determines a Start condition.

7 Allcommands must be preceded by a Start Data Transfer (C)A low-to-high transition of the SDA line while the clock(SCL) is high determines a Stop condition. Alloperations must end with a Stop Valid (D)The state of the data line represents valid data when,after a Start condition, the data line is stable for theduration of the high period of the clock data on the line must be changed during the lowperiod of the clock signal. There is one clock pulse perbit of data transfer is initiated with a Start condition andterminated with a Stop condition. The number of databytes transferred between Start and Stop conditions isdetermined by the master device and is, theoretically,unlimited (although only the last sixteen will be storedwhen doing a write operation). When an overwrite doesoccur it will replace data in a first-in first-out (FIFO) receiving device, when addressed, is obliged togenerate an Acknowledge signal after the reception ofeach byte.

8 The master device must generate an extraclock pulse which is associated with this device that acknowledges must pull down the SDAline during the acknowledge clock pulse in such a waythat the SDA line is stable-low during the high period ofthe acknowledge-related clock pulse. Of course, setupand hold times must be taken into account. Duringreads, a master must signal an end of data to the slaveby not generating an Acknowledge bit on the last bytethat has been clocked out of the slave. In this case, theslave ( 24LC16B ) will leave the data line high to enablethe master to generate the Stop 4-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUSNote:The 24LC16B does not generate anyAcknowledge bits if an internalprogramming cycle is in (A)(B)(D)(D)(A)(C)StartConditionAddress orAcknowledgeValidDataAllowedto ChangeStopCondition 2009-2016 Microchip Technology ADDRESSINGA control byte is the first byte received following theStart condition from the master device (Figure 5-1).

9 The control byte consists of a four-bit control the 24LC16B , this is set as 1010 binary for readand write operations. The next three bits of the controlbyte are the Block Select bits (B2, B1, B0). They areused by the master device to select which of the eight256 word-blocks of memory are to be bits are, in effect, the three Most Significant bits(MSb) of the word address. It should be noted that theprotocol limits the size of the memory to eight blocksof 256 words, therefore, the protocol can support onlyone 24LC16B per last bit of the Control byte defines the operation tobe performed. When set to 1 , a read operation isselected. When set to 0 , a write operation is the Start condition, the 24LC16B monitorsthe SDA bus, checking the device type identifier beingtransmitted and, upon receiving a 1010 code, theslave device outputs an Acknowledge signal on theSDA line. Depending on the state of the R/W bit, the24LC16B will select a read or write 5-1:CONTROL BYTE ALLOCATION FIGURE 5-2:ADDRESS SEQUENCE BIT ASSIGNMENTSO perationControl CodeBlock SelectR/WRead1010 Block Address1 Write1010 Block Address01010B2 B1 B0R/WACKS tart BitRead/Write BitSSlave AddressAcknowledge BitControl CodeBlockSelect Bits1010B2B1B0R/WA7A0 Control ByteAddress Low ByteControlCodeBlockSelectBits24LC16 BDS20002213B-page 8 2009-2016 Microchip Technology WriteFollowing the Start condition from the master, thedevice code (four bits), the block address (three bits)and the R/W bit, which is a logic low, are placed ontothe bus by the master transmitter.

10 This indicates to theaddressed slave receiver that a byte with a wordaddress will follow once it has generated anAcknowledge bit during the ninth clock , the next byte transmitted by the master isthe word address and will be written into the AddressPointer of the 24LC16B . After receiving anotherAcknowledge signal from the 24LC16B , the masterdevice will transmit the data word to be written into theaddressed memory location. The 24LC16 Backnowledges again and the master generates a Stopcondition. This initiates the internal write cycle and,during this time, the 24LC16B will not generateAcknowledge signals (Figure 6-1). Write The write control byte, word address and the first databyte are transmitted to the 24LC16B in the same wayas in a byte write. However, instead of generating aStop condition, the master transmits up to 16 data bytesto the 24LC16B , which are temporarily stored in theon-chip page buffer and will be written into memoryonce the master has transmitted a Stop receipt of each word, the four lower-orderAddress Pointer bits are internally incremented by higher-order 7 bits of the word address remainconstant.