256 10 Transceiver PHY User Guide - Altera

1 Intel Arria 10 Transceiver PHYUser GuideUpdated for Intel Quartus Prime Design Suite: FeedbackUG-01143 | document on the web: PDF | HTMLC ontents1. Arria 10 Transceiver PHY Overview .. Device Transceiver Arria 10 GX Device Transceiver Intel Arria 10 GT Device Transceiver Arria 10 GX and GT Device Package Details .. Arria 10 SX Device Transceiver Arria 10 SX Device Package Transceiver PHY Architecture Transceiver Bank PHY Layer Transceiver Transceiver Phase-Locked Clock Generation Block (CGB).

2 Intel Arria 10 Transceiver PHY Overview Revision 302. Implementing Protocols in Arria 10 Transceiver Design IP Transceiver Design Select and Instantiate the PHY IP Configure the PHY IP Generate the PHY IP Select the PLL IP Configure the PLL IP Generate the PLL IP Core .. Reset Controller .. Create Reconfiguration Connect the PHY IP to the PLL IP Core and Reset Connect Datapath .. Make Analog Parameter Settings .. Compile the Verify Design Arria 10 Transceiver Protocols and PHY IP Using the Arria 10 Transceiver Native PHY IP General and Datapath Parameters.

3 PMA Enhanced PCS Parameters .. Standard PCS PCS Direct .. Dynamic Reconfiguration PMA Enhanced PCS Standard PCS IP Core File Unused Transceiver RX Unsupported Arria 10 Transceiver PHY user GuideSend Metaframe Format and Framing Layer Control Interlaken Configuration Clocking and How to Implement Interlaken in Arria 10 Design Native PHY IP Parameter Settings for Gigabit Ethernet (GbE) and GbE with IEEE 10 GBASE-R, 10 GBASE-R with IEEE 1588v2, and 10 GBASE-R with 10 GBASE-KR PHY IP Core.

4 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP 1 Multi-rate Ethernet PHY Intel FPGA IP XAUI PHY IP PCI Express (PIPE).. Transceiver Channel Datapath for Supported PIPE How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 How to Implement PCI Express (PIPE) in Arria 10 Native PHY IP Parameter Settings for PIPE .. fPLL IP Parameter Core Settings for ATX PLL IP Parameter Core Settings for Native PHY IP Ports for fPLL Ports for ATX PLL Ports for Preset Mappings to TX How to Place Channels for PIPE PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Using Transceiver Toolkit (TTK)/System Console/ReconfigurationInterface to manually tune Arria 10 PCIe designs (Hard IP(HIP) and PIPE)(For debug only).

5 Transceiver Channel Datapath and Clocking for Supported Features for CPRI .. Word Aligner in Manual Mode for How to Implement CPRI in Arria 10 Native PHY IP Parameter Settings for Other Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurationsof Enhanced Using the Basic/Custom, Basic/Custom with Rate Match Configurations ofStandard Design Considerations for Implementing Arria 10 GT How to Implement PCS Direct Transceiver Configuration Simulating the Transceiver Native PHY IP NativeLink Simulation Scripting IP Custom Simulation Implementing Protocols in Intel Arria 10 Transceivers Revision PLLs and Clock FeedbackIntel Arria 10 Transceiver PHY user Transmit PLLs Spacing Guideline when using ATX PLLs and ATX CMU Input Reference Clock

6 Dedicated Reference Clock Receiver Input PLL Cascading as an Input Reference Clock Reference Clock Global Clock or Core Clock as an Input Reference Transmitter Clock x1 Clock x6 Clock xN Clock GT Clock Clock Generation FPGA Fabric- Transceiver Interface Transmitter Data Path Interface Receiver Data Path Interface Unused/Idle Clock Line Channel PMA PMA and PCS PCS Bonding Channels Placement Selecting Channel Bonding Skew PLL Feedback and Cascading Clock Using PLLs and Clock Non-bonded Bonded Implementing PLL Mix and Match Timing Closure PLLs and Clock Networks Revision Resetting Transceiver When Is Reset Required?

7 Transceiver PHY How Do I Reset?.. Model 1: Default Model 2: Acknowledgment Transceiver Blocks Affected by Reset and Powerdown Using the Transceiver PHY Reset Parameterizing the Transceiver PHY Reset Controller Transceiver PHY Reset Controller Transceiver PHY Reset Controller Transceiver PHY Reset Controller Resource Using a user -Coded Reset user -Coded Reset Controller Combining Status or PLL Lock Signals .. Timing Constraints for Bonded PCS and PMA 455 ContentsIntel Arria 10 Transceiver PHY user GuideSend Resetting Transceiver Channels Revision Arria 10 Transceiver PHY Arria 10 PMA Transmitter Receiver Clock Data Recovery (CDR)

8 Arria 10 Enhanced PCS Transmitter Receiver Arria 10 Standard PCS Transmitter Receiver Arria 10 PCI Express Gen3 PCS Transmitter Receiver PIPE Intel Arria 10 Transceiver PHY Architecture Revision Reconfiguration Interface and Dynamic Reconfiguration .. Reconfiguring Channel and PLL Interacting with the Reconfiguration Reading from the Reconfiguration Writing to the Reconfiguration Configuration Multiple Reconfiguration Embedded Reconfiguration Recommendations for Dynamic Steps to Perform Dynamic Direct Reconfiguration Native PHY IP or PLL IP Core Guided Reconfiguration Reconfiguration Flow for Special Switching Transmitter PLL.

9 Switching Reference Changing PMA Analog Changing VOD, Pre-emphasis Using Direct Reconfiguration Changing CTLE Settings in Manual Mode Using Direct Reconfiguration CTLE Settings in Triggered Adaptation Enabling and Disabling Loopback Modes Using Direct Reconfiguration Ports and Dynamic Reconfiguration Interface Merging Across Multiple IP Embedded Debug Native PHY Debug Master Optional Reconfiguration Using Data Pattern Generators and 562 ContentsSend FeedbackIntel Arria 10 Transceiver PHY user Using PRBS Data Pattern

10 Generator and Using Pseudo Random Pattern Timing Closure Unsupported Arria 10 Transceiver Register Reconfiguration Interface and Dynamic Revision 5767. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine .. Calibration Avalon Memory-Mapped Interface Arbitration Transceiver Channel Calibration Fractional PLL Calibration ATX PLL Calibration Capability Rate Switch Flag Power-up user Recalibration After Transceiver Reference Clock Frequency or Data Calibration ATX PLL Fractional PLL CDR/CMU PLL PMA Calibration Revision Analog Parameter Making Analog Parameter Settings using the Assignment Updating Quartus Settings File with the Known Analog Parameter