5. CMOS Operational Amplifiers - IMS

1 5. CMOS Operational AmplifiersAnalog design for CMOS VLSI SystemsFranco Maloberti5. CMOS Operational Amplifiers1 Analog design for CMOS VLSI SystemsFranco MalobertiBasic op-ampThe ideal Operational amplifier is a voltage controlledvoltage source with infinite gain, infinite input impedanceand zero output op-amp is always used in feedback CMOS Operational Amplifiers2 Analog design for CMOS VLSI SystemsFranco MalobertiTypical feedback configuration V0=V2Z4Z3+Z4Z1+Z2Z1 V1Z2Z1 The error due to the finite gain is proportional to 1 / A0. Thiserror must be smaller than the error due to impedancemismatch. V0=V2Z4Z3+Z4Z1+Z2Z1 V1Z2Z1 1+Z1+Z2A0Z1 Finite gain effect:5. CMOS Operational Amplifiers3 Analog design for CMOS VLSI SystemsFranco MalobertiOTAIf impedances are implemented with capacitors andswitches, after a transient, the load of the op-amp is madeof pure capacitors.

2 The behavior of the circuit does notdepend on the output resistance of the op-amp and stageswith high output resistance ( Operational transconductanceamplifiers) can be CMOS Operational Amplifiers4 Analog design for CMOS VLSI SystemsFranco MalobertiTransient Vi(0+)=VinC1C1+C//C0 Vo(0+)=Vi(0+)CC0+C Vi( )=VinC1+CC1+C(1+gmr0) Vo( )= Vi( ) gm r0 C0gm5. CMOS Operational Amplifiers5 Analog design for CMOS VLSI SystemsFranco MalobertiPerformance characteristicsActual op-amps deviate from the ideal behavior. Thedifferences are described by the differential gain:It is the open-loop voltage gain measured at DC with asmall differential input signal. Typically Ad = 80 100 CMOS Operational Amplifiers6 Analog design for CMOS VLSI SystemsFranco MalobertiCommon mode gain:It is the open-loop voltage gain with a small signal appliedto both the input terminals.

3 Acm = 20 40 mode rejection ratio:It is defined as the ratio between the differential gain andthe common mode gain. Typically CMRR = 40 80 CMOS Operational Amplifiers7 Analog design for CMOS VLSI SystemsFranco MalobertiPower supply rejection ratio:If a small signal is applied in series with the positive (ornegative) power supply, it is transferred to the output with agiven gain Aps+ (or Aps-).The ratios between differential gain and power supply gainsfurnish the two :PSRR = 90 dB (DC)PSRR = 60 dB (1 kHz)PSRR = 30 dB (100 kHz)5. CMOS Operational Amplifiers8 Analog design for CMOS VLSI SystemsFranco MalobertiInput offset voltage:In real circuits if the two input terminals are set at the samevoltage the output saturates close to VDD or to common mode range:It is the maximum range of the common-mode input voltagewhich do not produce a significant variation of thedifferential |Vos| = 4 6 CMOS Operational Amplifiers9 Analog design for CMOS VLSI SystemsFranco MalobertiOutput voltage swing:It is the swing of the output node without generating adefined amount of harmonic input noise:The noise performances can be described in terms of anequivalent voltage source at the input of the vn = 40 50 nV/ Hz at 1 kHz,in a wide band (1 MHz) it results 10 50 V CMOS Operational Amplifiers10 Analog design for CMOS VLSI SystemsFranco MalobertiUnity gain frequency.

4 It is the frequency where the open-loop gain is zero. It isalso the -3 dB bandwidth in unity-gain closed loopconditions. Typically fT = 200 margin:It is the phase shift of the small-signal differential gainmeasured at the unity gain frequency. A phase marginsmaller than 60 causes ringing in the output CMOS Operational Amplifiers11 Analog design for CMOS VLSI SystemsFranco MalobertiSlew rate:It is the maximum slope of the output voltage. Usually it ismeasured in the buffer configuration. The positive slew ratecan be different from the negative slew rate. Typically SR =50 200 V/ s (lower values for micropower operation).Settling time:The settling time is the time required to settle the outputwithin a given range (usually ) of the final dissipation:It depends on speed and bandwidth , for V supply, it is around 1 CMOS Operational Amplifiers12 Analog design for CMOS VLSI SystemsFranco MalobertiTypical parameters of a m OTA m22000 Silicon areamW1 Power dynamic common mode voltagekHz1 Corner frequencynV/ Hz100 Input referred noise (white)dB30 PSRR @ 100 kHzdB60 PSRR @ 1 kHzdB90 PSRR @ DCns300 Settling time: 1 V, CL = 4 pFV/ s3 Slew-rateMHz100 BandwidthmV4-6 OffsetdB40 CMRRdB80DC gainUnitValueFeature5.

5 CMOS Operational Amplifiers13 Analog design for CMOS VLSI SystemsFranco MalobertiBasic architecture 1st gain stage differential to single-ended converter 2nd gain stage output stage (to reduce the output impedance)Key requirements: absolute stability in unity gain closed-loop conditionswhen driving maximum load. minimum number of gain CMOS Operational Amplifiers14 Analog design for CMOS VLSI SystemsFranco MalobertiTwo-stage op-ampKey design issues: open-loop differential gain dc offset power supply rejection (PSRR)5. CMOS Operational Amplifiers15 Analog design for CMOS VLSI SystemsFranco MalobertiOpen-loop differential gain:The gain is obtained by multiplying the gains of the low frequency the gain is inversely proportional to thebias current. Av=A1A2=gm1(gds2+gds4)gm5(gds5+gds6)= =22 n pCox( n+ p)2WL 1WL 5WL BWL 6WL 71 IBias5.

6 CMOS Operational Amplifiers16 Analog design for CMOS VLSI SystemsFranco MalobertiCommon mode dc gain:Applying the same signal to both inputs the circuit becomessymmetrical and can be studied considering half circuit. ACM=ACM1 ACM2= gds72gm1 gm5gds5+gds6 CMRR=AvACM=2gm1gm3gds7(gds2+gds4)5. CMOS Operational Amplifiers17 Analog design for CMOS VLSI SystemsFranco MalobertiOffset:The offset is composed of two terms: systematic offset random offsetThe systematic offset can be reduced to zero with acareful design . A necessary condition to have zerosystematic offset, is that the currents of M5 and M6 areequal, when the inputs are connected to the same all the transistors in saturation this condition is: IBiasWL()6WL()B=IBiasWL()7WL()BWL()5WL() 3 WL()3WL()6=12WL()7WL()55. CMOS Operational Amplifiers18 Analog design for CMOS VLSI SystemsFranco MalobertiThe random offset is due to the geometrical mismatchingand process dependent inaccuracies.

7 Vos=Vos12+Vos2A1 2 When we refer the offset of the second stage at the inputterminal we have to divide it by the gain of the first the two offsets are uncorrelated we have:The total offset is dominated by the offset of the CMOS Operational Amplifiers19 Analog design for CMOS VLSI SystemsFranco MalobertiWe study the effect of a mismatch between M3 and M4:mirror factor (1 + ) instead of 1. IBias2 gm1 Vos12 1+ ()=IBias2+gm2 Vos12 Vos1 I1gm1 5. CMOS Operational Amplifiers20 Analog design for CMOS VLSI SystemsFranco MalobertiMOS: I1gm1=VGS1 VTh2=150 300 mV(in sub-threshold) I1gm1=nVT=nkTq(in saturation)BJT: I1gm1 26 mVAssuming = :Vos,BJT = mVVos,MOS = 3 mV5. CMOS Operational Amplifiers21 Analog design for CMOS VLSI SystemsFranco MalobertiPower supply rejection:A signal on the positive bias line determines a modulationin the reference current, which, in turn, gives an equalmodulation of the currents in M5 and M6, if the condition ofthe zero systematic offset is CMOS Operational Amplifiers22 Analog design for CMOS VLSI SystemsFranco MalobertiThe spur signal v+n affects the currents of M5 and M6.

8 In,6W/L()6=in,7W/L()7= CoxVGS,MB VTh() vn+ vo,n,1=in,totW/L()6W/L()B 12W/L()5W/L()7W/L()4W/L()B 1gds6++gds7 vo,n,1=in,RefW/L()6W/L()B1gm5b) high frequency:a) low frequency:5. CMOS Operational Amplifiers23 Analog design for CMOS VLSI SystemsFranco MalobertiPower supply rejection at low frequency vo,tot()2=gds6 gm5(1 k+)2gm3rds3gds5+gds6 vn+()2+gds6 gm5k 2gm3rds3gds5+gds6 vn ()25. CMOS Operational Amplifiers24 Analog design for CMOS VLSI SystemsFranco MalobertiEffect of external components on PSRR5. CMOS Operational Amplifiers25 Analog design for CMOS VLSI SystemsFranco MalobertiFrequency response andcompensation A two-stage scheme with poles in the same frequencyrange needs compensation. A single pole system is always stable. Strategy: Approach the single pole performance bysplitting the two poles CMOS Operational Amplifiers26 Analog design for CMOS VLSI SystemsFranco MalobertiMiller capacitance moves p1 at lower feedback moves p2 at higher signal equivalent circuit for two-stage op-amp.

9 V0vin=gm1R1R2gm2 sCc1+sR1R2gm2Cc+s2R1R2C1C2+(C1+C2)Cc[] v1(g1+sC1)+(v1 v0)sCc+gm1vin=0 v0(g2+sC2)+(v0 v1)sCc+gm2v1=05. CMOS Operational Amplifiers27 Analog design for CMOS VLSI SystemsFranco MalobertiThe circuit has two poles and a zero in the right half plane. p1 1R1R2gm2Cc p2 gm2 CcC1C2+(C1+C2)Ccsince in practice Cc > C1, Cc C2, gm1 > 1/R1, gm2 > 1/R2 itresults: z=gm2Cc p1<<1R1C1 p2 gm2C2>>1R2C2 Assuming p1 as dominant, the unity gain angular frequencyis: T=p1A0 1R1R2gm2 Ccgm1gm2R1R2=gm1Cc5. CMOS Operational Amplifiers28 Analog design for CMOS VLSI SystemsFranco MalobertiThe locations of the second pole p2 and of the zero withrespect to T are derived by considering: p2 T=gm2 Ccgm1C2for stability > 2 to 4 z T=gm2gm1 The phase shift given by thezero is also negative andcan worsen the phasemargin. It must be locatedfar from the unity CMOS Operational Amplifiers29 Analog design for CMOS VLSI SystemsFranco Malobertiif Cc > C2 and gm2 > gm1 The right half-plane worsen the phase margin.

10 In bipolar technology gm2 >> gm1 because the current inthe second stage is normally higher than the one in thefirst CMOS Operational Amplifiers30 Analog design for CMOS VLSI SystemsFranco Maloberti In CMOS technology gm2 gm1 because they areproportional to the square root of I and W/L; moreover,the transconductance of the input pair must be high inorder to reduce their thermal noise contribution. In real situations the obtainable phase margin does notguarantee the right half-plane zero: unity gain buffer zero nulling resistor unity gain current amplifierThe zero is due to a signal feedforwardto a point that is 180 out of CMOS Operational Amplifiers31 Analog design for CMOS VLSI SystemsFranco MalobertiSolution 1: Eliminate feedforward with source followerDisadvantages: Area Power dissipation Actually it creates a doublet in the feedback not stable.