64-Kbit serial I²C bus EEPROM - STMicroelectronics

1 This is information on a product in full production. March 2018DS6638 Rev 361/54M24C64-W m24c64 -R m24c64 -F m24c64 -DF64-Kbit serial I C bus EEPROM Datasheet - production dataFeatures compatible with all I2C bus modes: 1 MHz 400 kHz 100 kHz Memory array: 64 Kbit (8 Kbyte) of EEPROM Page size: 32 byte Additional Write lockable page ( m24c64 -D order codes) Single supply voltage: V to V over 40 C / +85 C V to V over 0 C / +85 C Write: Byte Write within 5 ms Page Write within 5 ms Random and sequential Read modes Write protect of the whole memory array Enhanced ESD/Latch-Up protection More than 4 million Write cycles More than 200-years data retentionPackages PDIP8 ECOPACK2 SO8 ECOPACK2 TSSOP8 ECOPACK2 UFDFPN ECOPACK2 WLCSP ECOPACK2 Unsawn wafer (each die is tested)SO8 (MN)150 mil widthTSSOP8 (DW)169 mil widthUFDFPN8 (MC)DFN8 - 2x3 mmWLCSP (CS)Thin WLCSP (CT)UFDFPN5 (MH)DFN5 mm PDIP8 (BN)WLCSP(CU)Unsawn m24c64 -R m24c64 -F m24c64 -DF2/54DS6638 Rev 36 Contents1 Description.

2 62 Signal description .. Clock (SCL) .. Data (SDA) .. Enable (E2, E1, E0) .. Control (WC) .. (ground) .. voltage (VCC) .. supply voltage (VCC) .. conditions .. reset .. conditions .. 103 Memory organization .. 114 Device operation .. condition .. condition .. input .. bit (ACK) .. addressing .. 145 Instructions .. operations .. Write .. Write .. Identification Page ( m24c64 -D only) .. Identification Page ( m24c64 -D only) .. (Error Correction Code) and Write cycling .. Write delays by polling on ACK .. operations .. Address Read .. 21DS6638 Rev 363/54M24C64-W m24c64 -R m24c64 -F Address Read.

3 Read .. Identification Page ( m24c64 -D only) .. the lock status ( m24c64 -D only) .. 226 Initial delivery state .. 237 Maximum rating .. 248DC and AC parameters .. 259 Package information .. (DFN5) package information .. (DFN8) package information .. package information .. package information .. package information .. ultra thin package information .. package information .. thin package information .. 4510 Ordering information .. 4711 Revision history .. 50 List of tablesM24C64-W m24c64 -R m24c64 -F m24c64 -DF4/54DS6638 Rev 36 List of tablesTable names .. 6 Table 4-bump signals vs. bump position.. 7 Table 5-bump signals vs.

4 Bump position.. 8 Table 8-bump signals vs bump position .. 8 Table select code .. 14 Table significant address byte .. 15 Table significant address byte .. 15 Table maximum ratings .. 24 Table conditions (voltage range W) .. 25 Table conditions (voltage range R) .. 25 Table conditions (voltage range F) .. 25 Table measurement conditions.. 25 Table parameters.. 26 Table performance .. 26 Table cell data retention .. 26 Table characteristics ( m24c64 -W, device grade 6) .. 27 Table characteristics ( m24c64 -R device grade 6) .. 28 Table characteristics ( m24c64 -F, m24c64 -DF, device grade 6) .. 29 Table kHz AC characteristics.. 30 Table MHz AC characteristics.

5 31 Table - mm, mm thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data .. 34 Table 2x3 mm, thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data .. 36 Table 3 x mm, mm pitch, 8-lead thin shrink small outline, package mechanical data .. 37 Table mm, 8-lead plastic small outline, 150 mils body width, package mechanical data .. 38 Table 8-pin plastic DIP, mm lead frame, package mechanical data.. 40 Table Thin WLCSP- 4-bump, x mm, wafer level chip scale package mechanical data.. 41 Table 5-bump, x mm, mm pitch wafer level chip scale package mechanical data.

6 44 Table WLCSP- 8-bump, x mm, wafer level chip scale package mechanical data .. 46 Table information scheme .. 47 Table information scheme (unsawn wafer) .. 48 Table revision history .. 50DS6638 Rev 365/54M24C64-W m24c64 -R m24c64 -F m24c64 -DFList of figures5 List of figuresFigure diagram .. 6 Figure package connections, top view .. 6 Figure (DFN5) package connections .. 7 Figure 4 bump ultra thin package connections .. 7 Figure 5-bump connections ( m24c64 -FCS6TP/K) .. 7 Figure 8-bump thin connections ( m24c64 -DFCT6TP/K) .. 8 Figure enable inputs connection .. 9 Figure diagram .. 11 Figure bus protocol .. 12 Figure mode sequences with WC = 0 (data write enabled).

7 16 Figure mode sequences with WC = 1 (data write inhibited) .. 17 Figure cycle polling flowchart using ACK .. 19 Figure mode sequences .. 20 Figure measurement I/O waveform .. 26 Figure Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz.. 32 Figure Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1 MHz .. 32 Figure waveforms .. 33 Figure mm, mm thickness, ultra thin fine pitch dual flat package, no lead - package outline .. 34 Figure - 5-lead, mm, mm thickness, ultra thin fine pitch dual flat package, no lead recommended footprint.

8 35 Figure 2x3 mm, thickness, ultra thin fine pitch dual flat package, no lead - package outline .. 36 Figure mm, mm pitch, 8-lead thin shrink small outline, package outline.. 37 Figure mm, 8-lead plastic small outline, 150 mils body width, package outline . 38 Figure mm, 8-lead plastic small outline, 150 mils body width, package recommended footprint .. 39 Figure 8-pin plastic DIP, mm lead frame, package outline .. 40 Figure Thin WLCSP- 4-bump, x mm,wafer level chip scale package outline .. 41 Figure WLCSP- 4-bump, x mm, wafer level chip scale package recommended footprint .. 42 Figure 5-bump, x mm, mm pitch wafer level chip scale ( m24c64 -FCS6TP/K)- package outline.

9 43 Figure - 5-bump, x mm, mm pitch wafer level chip scale recommended footprint .. 44 Figure WLCSP- 8-bump, x mm, wafer level chip scale package outline.. 45 Figure WLCSP- 8-bump, x mm, wafer level chip scale package recommended footprint .. 46 DescriptionM24C64-W m24c64 -R m24c64 -F m24c64 -DF6/54DS6638 Rev 361 DescriptionThe m24c64 is a 64-Kbit I2C- compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 8 K 8 an ambient temperature range of -40 C / +85 C, the m24c64 -W can operate with a supply voltage from V to V, the m24c64 -R can operate with a supply voltage from V to V, and the m24c64 -F and m24c64 -DF can operate with a supply voltage from V to V ( the m24c64 -F can also operate down to V, under some restricting conditions).

10 The m24c64 -D offers an additional page, named the Identification Page (32 byte). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only 1. Logic diagram Figure 2. 8-pin package connections, top view1. See Section 9: Package information for package dimensions, and how to identify pin 1 Table 1. Signal namesSignal nameFunctionDirectionE2, E1, E0 Chip EnableInputSDAS erial DataI/OSCLS erial ClockInputWCWrite ControlInputVCCS upply voltage-VSSG round-$, I ( ( 6'$9&&0 [[[:&6&/966$, I6'$9666&/:&( ( 9&&( DS6638 Rev 367/54M24C64-W m24c64 -R m24c64 -F m24c64 -DFDescription53 Figure 3.)))))]]]