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7 Series FPGAs Data Sheet: Overview (DS180) - Xilinx

DS180 ( ) February 27, Specification1 Copyright 2010 2018 Xilinx , Inc., Xilinx , the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective DescriptionXilinx 7 Series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 Series FPGAs include: Spartan -7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factor packaging for smallest PCB footprint . Artix -7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput.

packaging for smallest PCB footprint. † Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitive applications. † Kintex®-7 Family: Optimized for best price-performance with a 2X

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Transcription of 7 Series FPGAs Data Sheet: Overview (DS180) - Xilinx

1 DS180 ( ) February 27, Specification1 Copyright 2010 2018 Xilinx , Inc., Xilinx , the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective DescriptionXilinx 7 Series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 Series FPGAs include: Spartan -7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factor packaging for smallest PCB footprint . Artix -7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput.

2 Provides the lowest total bill of materials cost for high-throughput, cost-sensitive applications. Kintex -7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs . Virtex -7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI) on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 Series FPGAs enable an unparalleled increase in system performance with Tb/s of I/O bandwidth, 2 million logic cell capacity, and TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs. Summary of 7 Series FPGA Features Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory. 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.

3 High-performance SelectIO technology with support for DDR3 interfaces up to 1,866 Mb/s. High-speed serial connectivity with built-in multi-gigabit transceivers from 600 Mb/s to max. rates of Gb/s up to Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces. A user configurable analog interface (XADC), incorporating dual 12-bit 1 MSPS analog-to-digital converters with on-chip thermal and supply sensors. DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering. Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter. Quickly deploy embedded processing with MicroBlaze processor. Integrated block for PCI Express (PCIe), for up to x8 Gen3 Endpoint and Root Port designs. Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.

4 Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option. Designed for high performance and lowest power with 28 nm, HKMG, HPL process, core voltage process technology and core voltage option for even lower Series FPGAs Data Sheet: OverviewDS180 ( ) February 27, 2018 Product SpecificationTable 1:7 Series Families ComparisonMax. CapabilitySpartan-7 Artix-7 Kintex-7 Virtex-7 Logic Cells102K215K478K1,955 KBlock RAM(1) Slices 1607401,9203,600 DSP Performance(2)176 GMAC/s929 GMAC/s2,845 GMAC/s5,335 GMAC/sMicroBlaze CPU(3)260 DMIPs303 DMIPs438 DMIPs441 DMIPsTransceivers 163296 Transceiver Speed Gb/sSerial Bandwidth 211 Gb/s800 Gb/s2,784 Gb/sPCIe Interface x4 Gen2x8 Gen2x8 Gen3 Memory Interface800 Mb/s1,066 Mb/s1,866 Mb/s1,866 Mb/sI/O Pins400500500 1,200I/O OptionsLow-Cost, Wire-BondLow-Cost, Wire-Bond, Bare-Die Flip-ChipBare-Die Flip-Chip and High-Performance Flip-ChipHighest Performance Flip-ChipNotes: memory available in the form of distributed DSP performance numbers are based on symmetrical filter MicroBlaze CPU performance numbers based on microcontroller Series FPGAs Data Sheet: OverviewDS180 ( ) February 27, Specification2 Spartan-7 FPGA Feature SummaryTable 2.

5 Spartan-7 FPGA Feature Summary by DeviceDeviceLogic CellsCLBDSP Slices(2)Block RAM Blocks(3) CMTs(4)PCIeGTXADC BlocksTotal I/O Banks(5)Max User I/OSlices(1)Max Distributed RAM (Kb)18 Kb36 KbMax (Kb)XC7S66,000938701010518020002100XC7S1 512,8002,00015020201036020002100XC7S2523 ,3603,6503138090451,62030013150XC7S5052, 1608,150600120150752,70050015250XC7S7576 ,80012,000832140180903,24080018400XC7S10 0102,40016,0001,1001602401204,3208001840 0 Notes: 7 Series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb CMT contains one MMCM and one not include configuration Bank 3:Spartan-7 FPGA Device-Package Combinations and Maximum I/OsPackageCPGA196 CSGA225 CSGA324 FTGB196 FGGA484 FGGA676 Size (mm)8 x 813 x 1315 x 1515 x 1523 x 2327 x 27 Ball Pitch (mm) I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)HR I/O(1)XC7S6100100100XC7S15100100100XC7S2 5150150100XC7S50210100250XC7S75338400XC7 S100338400 Notes: = High-range I/O with support for I/O voltage from to Series FPGAs Data Sheet: OverviewDS180 ( ) February 27, Specification3 Artix-7 FPGA Feature SummaryTable 4.

6 Artix-7 FPGA Feature Summary by DeviceDeviceLogic CellsConfigurable Logic Blocks (CLBs)DSP48E1 Slices(2)Block RAM Blocks(3)CMTs(4)PCIe(5)GTPsXADC BlocksTotal I/O Banks(6)Max User I/O(7)Slices(1)Max Distributed RAM (Kb)18 Kb36 KbMax (Kb)XC7A12T12,8002,000171404020720312131 50XC7A15T16,6402,60020045502590051415250 XC7A25T23,3603,6503138090451,62031413150 XC7A35T33,2805,20040090100501,8005141525 0XC7A50T52,1608,150600120150752,70051415 250XC7A75T75,52011,8008921802101053,7806 1816300XC7A100T101,44015,8501,1882402701 354,86061816300XC7A200T215,36033,6502,88 874073036513,14010116110500 Notes: 7 Series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb CMT contains one MMCM and one FPGA Interface Blocks for PCI Express support up to x4 Gen not include configuration Bank number does not include GTP 5:Artix-7 FPGA Device-Package Combinations and Maximum I/OsPackage(1)CPG236 CPG238 CSG324 CSG325 FTG256 SBG484 FGG484(2)FBG484(2)FGG676(3)FBG676(3)FFG1 156 Size (mm)10 x 1010 x 1015 x 1515 x 1517 x 1719 x 1923 x 2323 x 2327 x 2727 x 2735 x 35 Ball Pitch (mm) (4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I /OGTPI/OGTP(4)I/OGTPI/OGTP(4)I/OGTPI/OGT PI/OHR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)H R(5)HR(5)HR(5)HR(5)XC7A12T21122150XC7A15 T21060210415001704250XC7A25T21124150XC7A 35T21060210415001704250XC7A50T2106021041 5001704250XC7A75T0210017042858300XC7A100 T0210017042858300XC7A200T428542858400165 00 Notes: packages listed are Pb-free (SBG, FBG, FFG with exemption 15).

7 Some packages are available in Pb in FGG484 and FBG484 are footprint compatible. in FGG676 and FBG676 are footprint transceivers in CP, CS, FT, and FG packages support data rates up to = High-range I/O with support for I/O voltage from to Series FPGAs Data Sheet: OverviewDS180 ( ) February 27, Specification4 Kintex-7 FPGA Feature SummaryTable 6:Kintex-7 FPGA Feature Summary by DeviceDeviceLogic CellsConfigurable Logic Blocks (CLBs)DSP Slices(2)Block RAM Blocks(3)CMTs(4)PCIe(5)GTXsXADC BlocksTotal I/O Banks(6)Max User I/O(7)Slices(1)Max Distributed RAM (Kb)18 Kb36 KbMax (Kb)XC7K70T65,60010,2508382402701354,860 61816300XC7K160T162,24025,3502,188600650 32511,70081818400XC7K325T326,08050,9504, 00084089044516,02010116110500XC7K355T356 ,16055,6505,0881,4401,43071525,740612416 300XC7K410T406,72063,5505,6631,5401,5907 9528,62010116110500XC7K420T416,96065,150 5,9381,6801,67083530,060813218400XC7K480 T477,76074,6506,7881,9201,91095534,38081 3218400 Notes: 7 Series FPGA slice contains four LUTs and eight flip-flops.

8 Only some slices can use their LUTs as distributed RAM or DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb CMT contains one MMCM and one FPGA Interface Blocks for PCI Express support up to x8 Gen not include configuration Bank number does not include GTX 7:Kintex-7 FPGA Device-Package Combinations and Maximum I/OsPackage(1)FBG484 FBG676(2)FFG676(2) FBG900(3)FFG900(3)FFG901 FFG1156 Size (mm)23 x 2327 x 2727 x 2731 x 3131 x 3131 x 3135 x 35 Ball Pitch (mm) (4)I/OGTX(4)I/OGTXI/OGTX(4)I/OGTXI/OGTXI /OGTXI/OHR(5)HP(6)HR(5)HP(6)HR(5)HP(6)HR (5)HP(6)HR(5)HP(6)HR(5)HP(6)HR(5)HP(6)XC 7K70T41851008200100XC7K160T4185100825015 08250150XC7K325T825015082501501635015016 350150XC7K355T243000XC7K410T825015082501 501635015016350150XC7K420T283800324000XC 7K480T283800324000 Notes: packages listed are Pb-free (FBG, FFG with exemption 15). Some packages are available in Pb in FBG676 and FFG676 are footprint in FBG900 and FFG900 are footprint transceivers in FB packages support the following maximum data rates: in FBG484; in FBG676 and FBG900.

9 Refer to Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182) for = High-range I/O with support for I/O voltage from to = High-performance I/O with support for I/O voltage from to Series FPGAs Data Sheet: OverviewDS180 ( ) February 27, Specification5 Virtex-7 FPGA Feature SummaryTable 8:Virtex-7 FPGA Feature SummaryDevice(1)Logic CellsConfigurable Logic Blocks (CLBs)DSP Slices(3)Block RAM Blocks(4)CMTs(5)PCIe(6)GTX GTH GTZXADC BlocksTotal I/O Banks(7)Max User I/O(8)SLRs(9)Slices(2)Max Distributed RAM (Kb)18 Kb36 KbMax (Kb)XC7V585T582,72091,0506,9381,260 1,590795 28,6201833600117850N/AXC7V2000T1,954,560 305,40021,5502,160 2,5841,29246,51224436001241,2004XC7VX330 T326,40051,0004,3881,1201,50075027,00014 20280114700N/AXC7VX415T412,16064,4006,52 52,1601,76088031,6801220480112600N/AXC7V X485T485,76075,9008,1752,8002,0601,03037 ,0801445600114700N/AXC7VX550T554,24086,6 008,7252,8802,3601,18042,480202080011660 0N/AXC7VX690T693,120108,30010,8883,6002, 9401,47052,92020308001201,000N/AXC7VX980 T979,200153,00013,8383,6003,0001,50054,0 001830720118900N/AXC7VX1140T 1,139,200178,00017,7003,3603,7601,88067, 68024409601221,1004XC7VH580T580,48090,70 08,8501,6801,88094033,84012204881126002X C7VH870T876,160136,90013,2752,5202,8201, 41050,76018307216163003 Notes: -7 FPGAs are also available to provide a fast, simple, and risk-free solution for cost reducing Virtex-7 T and Virtex-7 XT FPGA 7 Series FPGA slice contains four LUTs and eight flip-flops.

10 Only some slices can use their LUTs as distributed RAM or DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb CMT contains one MMCM and one T FPGA Interface Blocks for PCI Express support up to x8 Gen 2. Virtex-7 XT and Virtex-7 HT Interface Blocks for PCI Express support up to x8 Gen 3, with the exception of the XC7VX485T device, which supports x8 Gen not include configuration Bank number does not include GTX, GTH, or GTZ logic regions (SLRs) are the constituent parts of FPGAs that use SSI technology. Virtex-7 HT devices use SSI technology to connect SLRs with Gb/s Series FPGAs Data Sheet: OverviewDS180 ( ) February 27, Specification6 Table 9:Virtex-7 FPGA Device-Package Combinations and Maximum I/OsPackage(1)FFG1157 FFG1761(2)FHG1761(2)FLG1925 Size (mm)35 x x x 4545 x 45 Ball GTHI/OGTX GTHI/OGTXI/OHR(3)HP(4)HR(3)HP(4)HR(3)HP( 4)HR(3) HP(4)XC7V585T2000600360100750XC7V2000T36 008501601,200XC7VX330T020060002850650XC7 VX415T0200600XC7VX485T20006002800700XC7V X550 TXC7VX690T02006000360850XC7VX980 TXC7VX1140 TNotes: packages listed are Pb-free (FFG, FHG, FLG with exemption 15).


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