Achieving Higher ADC Resolution Using …

1 2008 Microchip Technology 1AN1152 INTRODUCTIONAn Analog-to-Digital Converter (ADC) is an active inter-face between the analog and digital signal chains in anembedded system. An ADC converts analog signalsinto digital signals in electronic systems. The key fea-ture of an ADC is the accuracy ( Resolution ) it offers. Thehigher the desired accuracy, the Higher the ADC ADC accuracy is achieved by designing hard-ware to quantize the analog signal amplitude into thedigital signal with a Higher code-word length. PracticalADCs have finite word effectively strike a balance between system costand accuracy, Higher conversion accuracy is achievedby oversampling the low- Resolution ADC integratedwithin a digital signal controller (DSC), and then pro-cessing the oversampled digital signal in softwarethrough a digital filter and a decimator. This processingscheme, which adds additional bits of accuracy to the12-bit ADC conversion in a dsPIC DSC, is explored inthis application OF OPERATIONAs previously mentioned, ADCs transform analogsignals into digital sample values.

2 Analog signalamplitude is quantized into digital code words with afinite word length. This process of quantizationintroduces noise in the signal called quantizationnoise . The smaller the word length, the greater thenoise noise can be reduced by adding more bitsinto the ADC hardware design. This noise can also bereduced in software by oversampling the ADC and thenprocessing the digital signal. The oversampling ADCmethod and a few associated terms are explained inthe following Voltage ResolutionVoltage Resolution of an ADC is defined as the ratio offull scale voltage range to the number of digital levelsthat are accommodated in that range. It is a measure ofthe accuracy of the ADC. The Higher the Resolution , thehigher the number of levels accommodated in thevoltage range and, consequently, the lower thequantization noise, as shown in Equation 1:Author:Jayanth Murthy MadapuraMicrochip Technology Resolution1 Least Significant bit (LSb) valuefull scale voltage range2N1 ---------------------------------------- ----------------voltslevel------------== where N is the number of bits or the word lengthAchieving Higher ADC Resolution Using OversamplingAN1152DS01152A-page 2 2008 Microchip Technology smallest ADC step represents one Least Signifi-cant bit (LSb) value.

3 For example, if the full scale mea-surement voltage range is 0 to 3 volts, and the ADC bitresolution is 12 bits, then the ADC voltage resolutioncan be calculated to be means the conversion of continuous voltages isnoise free if the continuous voltage is an integral multi-ple of the voltage Resolution . Any intermediate continu-ous voltage is rounded off to suit a voltage level that isan integral multiple of the voltage Resolution , as shownin Figure 1. This introduces quantization noise, asshown in Figure 2. FIGURE 1:FIGURE 2:The measure of the extent to which the signal iscorrupted with quantization noise after analog-to-digitalconversion is given by the signal-to-quantization Noise RatioSignal-to-Quantization Noise Ratio (SNRQ) is definedas the ratio of the root mean square value of the inputanalog signal to the root mean square value of thequantization noise.

4 The SNRQ of an ideal N-bit ADC isgiven by Equation 2:When the input analog signal is sinusoidal LF = ,then SNRQ is given by Equation 3:From Equation 3, it is clear that the improvement in theSNR of the ADC is dB per bit. The Higher the num-ber of bits associated with the ADC, the Higher theSNRQ. For example, the SNRQ-MAX of a 12-bit ADC dB and that of a 16-bit ADC is dB. Now wewill explore how the SNR can be improved withoutincreasing the word length of the ADC, Digital Filtering, Decimation and DitheringA cost-effective method of improving the Resolution ofthe ADC is developing software to suitably process theconverted analog-to-digital signal to achieve the sameeffect as a Higher Resolution Power Spectral Density (PSD) of the quantizationnoise with a flat spectrum, which gets added during ananalog-to-digital conversion (see Figure 3), is given byEquation 4:Original analog signalQuantized signalQuantization ()dB[]++=where, N is the number of bits or the word length, andLF is the loading factor, which is defined as the ratio ofthe root mean square value of the input analog voltageto the peak ADC input []+= +=PSDquantization noiselsb value()212fs---------------------------- -WHz-------= 2008 Microchip Technology 3AN1152 FIGURE 3.

5 POWER SPECTRAL DENSITY OF QUANTIZATION NOISE IN AN IDEAL ADCP ower spectral density representation of the signalafter an analog-to-digital conversion is seen inFigure 4:POWER SPECTRAL DENSITY OF SIGNAL COMPONENT QUANTIZATION NOISE IN AN IDEAL ADC AFTER ANALOG-TO-DIGITAL CONVERSIONOne way of reducing the PSD is by reducing thenumerator ( , the LSb value), which can be achievedby adding more bit Resolution to the ADC. Anothermethod of reducing PSD is by increasing the denomi-nator ( , by increasing the sampling frequency),which leads to oversampling . The power spectral den-sity representation of the signal after analog-to-digitalconversion and after oversampling is seen in Figure analog input signal is conveniently sampled at asampling rate (fOS) significantly Higher than the Nyquistrate, fN = 2B, with the help of the high sampling ratecapacity of the ADC present in the dsPIC digital 5:POWER SPECTRAL DENSITY OF SIGNAL COMPONENT QUANTIZATION NOISE IN AN IDEAL ADC AFTER ANALOG-TO-DIGITAL CONVERSION AND AFTER OVERSAMPLINGThe SNR improvement after oversampling is given byEquation 5:The overall SNR is given by Equation 6:Suppose we have a P-bit ADC and Q-bit ADC, Q>P,the sampling factor is calculated as shown inEquation 7.

6 Equation 8 shows how to achieve the SNR of a 16-bitADC Using a 12-bit quantization noisefS/20-fS/2 PSDPSD quantization noiseTotal quantization noisefS/20-fN/2 PSDS ignal componentBAABT otal quantization noisefOS/20-fOS/2 PSDS ignal componentfOS >> fN B A A BSNR oversampling10logfOSfN------- db[]= ++fOSfN------- db[]= ()=AN1152DS01152A-page 4 2008 Microchip Technology 8:The analog signal should be oversampled at a rate of256 times more than the Nyquist rate to achieve theSNR of a 16-bit ADC with a 12-bit oversampled analog-to-digital converted signal islow-pass filtered (see Figure 6) to alleviate the effectsof quantization noise. The digital low-pass filter can bemodeled as a FIR 6:POWER SPECTRAL DENSITY OF SIGNAL COMPONENT QUANTIZATION NOISE IN AN IDEAL ADC AFTER ANALOG-TO-DIGITAL CONVERSION AND AFTER oversampling WITH LOW-PASS FILTER RESPONSEA low-pass FIR filter is used to filter the quantizationnoise from the analog-to-digital converted signal.

7 Thecut-off frequency of the FIR filter used is fC. The orderof the FIR filter can be set to O, L = O+1 sampling frequency used can be set to K fN,where fN=2 filtering, the analog-to-digital converted signal ispassed through a decimation stage to downgrade therate, at which time the signal is sampled. The signalultimately obtained has a Higher SNR, which is close tothe SNR of a Q-bit ADC although a P-bit ADC wasemployed for analog-to-digital block diagram of all the associated stages isshown in Figure improvement in accuracy can be gained byadding an external dithering circuit before the is a technique used to minimize the ADCquantization noise by adding noise to the analog signalbefore passing it through the ADC. The periodicity ofthe quantization error in Figure 1 shows that it containsspectral harmonics, which yields the quantization noisehighly correlated.

8 Spectral harmonics make the filteringmore difficult and results in residual components. Dith-ering makes the resulting quantization noise more ran-dom with reduced levels of undesirable spectralharmonics. The simple dithering circuit consists of anoise diode and an amplification 7:BLOCK DIAGRAMSNR overall 16-bit ADCSNR overall 12-bit ADC with oversampling = ++ =+ quantization noisefOS/20-fOS/2 PSDS ignal componentLow-pass filteringBAABAnti-aliasingLow-PassAnalog FilterDigital Filterto reduceQuantizationNoiseDecimatorQuantiza tionNoise ADCfSInputAnalogSignalOutputDigitalSigna l 2008 Microchip Technology 5AN1152 APPLICATION EXAMPLEThis section describes an example of a real-worldapplication, upon which the techniques described inthis application note can be application circuit consists of a sensor (force, pres-sure, humidity, etc.), a conditioning circuit and thedsPIC DSC, as shown in Figure 8.

9 The conditioning circuit used is a three op amp instru-mentation amplifier as shown in Figure 9. Using a con-ditioning circuit, the two low-voltage signals from thedifferential output of the sensor are subtracted to pro-duce a single-ended output signal. The result of thissubtraction is amplified Using a certain amount of gainso that it matches the input range of the ADC. Theassociated equations are included in Figure 9. The implementation of the subtraction and gainfunctions are done so that the sensor signal is notcontaminated with additional errors and matches thevoltage range of the ADC. The amplified signal is fed tothe ADC pin of the dsPIC DSC. As previouslydiscussed, the dsPIC DSC does the oversampling ,filtering and decimation to achieve this application example, an FSG15N1A differentialoutput force sensor with a specific response time ( ,the time required for the force sensor output to risefrom 10% to 90% of the final value when subjected tochange in force) is used.

10 The anti-aliasing filters associated with the decimationstage and the conditioning circuit (if any) are designedto filter the force sensor signal, which is sampled at asampling frequency that is same as the responsefrequency = (1/response time). For example, if theresponse time is 1 ms, the sampling frequency must beat least 1 kHz. The cut-off frequency for the FIR anti-aliasing filter can be chosen to be slightly less than500 Hz, assuming that the force sensor reading isrecorded at a sampling frequency of 1 ADC is oversampled by a sampling factor,K= 256, to achieve the SNR rating of a 16-bit ADCfrom the 12-bit ADC signal. The ADC is oversampledusing the sampling frequency of fOS=256 fN=256kHz. An improvement of ~24 dB is expected Using 8:BLOCK DIAGRAM WITH dsPIC DIGITAL SIGNAL CONTROLLERFIGURE 9:CONDITIONING CIRCUIT: THREE OP AMP INSTRUMENTATION AMPLIFIERS ensorConditioningCircuitdsPIC Digital Signal ControllerA3 MCP604A1 MCP604A2 MCP604 VIN-VIN+R2 VOUTR4 VREFR1RF1RF2R3 RGwhere.