Advanced Digital Calibration Techniques for Data Converters

1 12/3/2014. Erik Jonsson School of Engineering & Computer Science Advanced Digital Calibration Techniques for data Converters Yun Chiu Erik Jonsson Distinguished Professor university of texas at dallas Presentation Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital -Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-ADC, sub-DAC, input). Two-ADC Equalization ( , split-ADC, ODC). Energy Efficiency and Trend Summary EECT 7326, Fall 2014 -2- Y. Chiu 1. 12/3/2014. Presentation Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital -Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-ADC, sub-DAC, input). Two-ADC Equalization ( , split-ADC, ODC). Energy Efficiency and Trend Summary EECT 7326, Fall 2014 -3- Y. Chiu What is A/D Conversion? CT, CA DT, DA.. VFS V t V nTs . LSB = = , Dout n = in = 2N in . t=nTs . N. 2 VFS . Quantization = division + normalization + truncation VFS is the Full-Scale range of ADC determined by Vref.

2 EECT 7326, Fall 2014 -4- Y. Chiu 2. 12/3/2014. Quantization Error (or Noise). N=3 N is large Dout 7 Vin >> , Vin is active 6 is uniformly distributed 5. P . 4. 3 Vin VFS VFS 1/ . 2 2 2. 1. 0.. -3 -2 - 0 2 3 - /2 0 /2. /2. 1 2. - . 2 2. 2 = . - /2. 2 .. d =. 12. "Random" quantization error is usually regarded as noise. Ref. [1]. EECT 7326, Fall 2014 -5- Y. Chiu Flash ADC Exhaustive Search Vi VFS Vi Strobe VFS. fs Massive parallelism 7. 7 . Very fast 6 Reference ladder 6 . consists of 2N equal 5. size resistors Encoder 5 . Dout .. Input is compared 2 to 2N-1 reference 1. voltages . 0 Throughput = fs Do 0 Complexity = 2N. 2N-1. comparators Flash ADC is rarely used for beyond 6-8 bits due to complexity. EECT 7326, Fall 2014 -6- Y. Chiu 3. 12/3/2014. Long Division (Decimal Case). 735. 4. = 183. r 3 . Dividend Divisor Quotient Remainder 183. 4 ) 735. 4 (1 4=4) 1 8 3. 33 (7 4=3) 400 ) 735 40 ) 335 4 ) 15. 32 (8 4=32). 400 320 12. 15 (33 32=1). 335 15 3. 12 (3 4=12). 3 (15 12=3) Step 1: Step 2: Step 3: 1st bit 2nd bit 3rd bit EECT 7326, Fall 2014 -7- Y.

3 Chiu Quantization (Binary Case). N = 3, FS = 1000, = 1000/8 = 125, Vin = 735. = . 1,0,1 r 110. V . Do = in 125. 735 . Vin LSB QN. Do 1 0. 500 ) 735 250 ) 235. 500 0. 235 235. Step 1: Step 2: Step 3: 1st bit 2nd bit 3rd bit The procedure is also known as "binary search". EECT 7326, Fall 2014 -8- Y. Chiu 4. 12/3/2014. Successive-Approximation (SAR) ADC. SAR = 1 comparator + 1 DAC + Digital logic EECT 7326, Fall 2014 -9- Y. Chiu Binary Search MSB Cycle N = 3, FS = 1 V, = V, Vin = V. Sampling .. VX = Vi ;. if VX > 0, MSB = 1, keep current VX VX;. otherwise, MSB = 0, restore VX VX + ;. EECT 7326, Fall 2014 - 10 - Y. Chiu 5. 12/3/2014. Binary Search MSB-1 Cycle N = 3, FS = 1 V, = V, Vin = V. Sampling .. VX = VX ;. if VX > 0, MSB-1 = 1, keep current VX VX;. otherwise, MSB-1 = 0, restore VX VX + ;. EECT 7326, Fall 2014 - 11 - Y. Chiu Binary Search MSB-2 Cycle N = 3, FS = 1 V, = V, Vin = V. Sampling .. VX = VX ;. if VX > 0, MSB-2 = 1, keep current VX VX;. otherwise, MSB-2 = 0, restore VX VX +.

4 EECT 7326, Fall 2014 - 12 - Y. Chiu 6. 12/3/2014. Quantization (Binary) Modified . N = 3, FS = 1000, = 1000/8 = 125, Vin = 735. = . 1,0,1 r 110. V . Do = in 125. 735 . Vin LSB QN. Do 1. 500 ) 940. 500. 440. Step 1: Step 2: Step 3: 1st bit 2nd bit 3rd bit Always use the same divisor but amplify the residue. EECT 7326, Fall 2014 - 13 - Y. Chiu Algorithmic (Cyclic) ADC. Fixed comparison threshold (VFS/2) + 1-b DAC + Residue Amplifier Modified "Binary Search". EECT 7326, Fall 2014 - 14 - Y. Chiu 7. 12/3/2014. Bit Cycles Vo bj=0 bj=1. VFS. 0 VFS/2 VFS VX. Comparison if VX < VFS/2, then bj = 0; otherwise, bj = 1. Residue generation Vo = 2 (VX - bj VFS/2). EECT 7326, Fall 2014 - 15 - Y. Chiu Pipelined ADC. Algorithmic ADC loop unrolled pipeline enables high throughput EECT 7326, Fall 2014 - 16 - Y. Chiu 8. 12/3/2014. Presentation Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital -Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-ADC, sub-DAC, input).

5 Two-ADC Equalization ( , split-ADC, ODC). Energy Efficiency and Trend Summary EECT 7326, Fall 2014 - 17 - Y. Chiu What happens with circuit offsets? Ideal RA offset CMP offset Vo Vo Vo b=0 b=1 b=0 b=1 Vos b=0 b=1. VFS VFS VFS. Vos 0 VFS/2 VFS Vi 0 VFS/2 VFS Vi 0 VFS/2 VFS Vi Do Do Do 0 VFS/2 VFS Vi 0 VFS/2 VFS Vi 0 VFS/2 VFS Vi Nearly zero tolerance on circuit offset errors!! EECT 7326, Fall 2014 - 18 - Y. Chiu 9. 12/3/2014. Over-range & Under-range Comparators Vo Vo bj=0 bj=1 bj=0 bj=1 Bj+1=2. VFS VFS. Bj+1=1 Bj+1=1. VFS/2 VFS/2. Bj+1=0 Bj+1=0. 0 VFS/2 VFS Vi 0 VFS/2 VFS Vi Bj+1=-1. Do Do 11 11. 10 10. 01 01. 00 00. 0 VFS/2 VFS Vi 0 VFS/2 VFS Vi 1 CMP 3 CMPs EECT 7326, Fall 2014 - 19 - Y. Chiu Redundancy ( DEC or RSD). Original w/ Redundancy 4-level (2-bit) DAC required instead of 2-level (1-bit) DAC. EECT 7326, Fall 2014 - 20 - Y. Chiu 10. 12/3/2014. Complementary Analog- Digital Information Vo 1 bit Bj+1=2. bj=0 bj=1 Max tolerance of VFS. Bj+1=1 comparator offset is 1 FS VFS/4 simple VFS/2.

6 Comparators Bj+1=0. Key to understand 0 VFS/2 VFS Vi redundancy: Bj+1=-1. Vo Do b j =0. 2. 11. 10 VFS Vo 01. Vi = b j +. 2 2. 00. 0 VFS/2 VFS Vi EECT 7326, Fall 2014 - 21 - Y. Chiu From 1-bit to Architecture FS. bit 1-bit Vo b =0. No redundancy 2. EECT 7326, Fall 2014 - 22 - Y. Chiu 11. 12/3/2014. From 1-bit to Architecture FS. FS. bit bit Vo Vo b =0 b =0. 2 2. EECT 7326, Fall 2014 - 23 - Y. Chiu From 1-bit to Architecture Vo Vo b =0 b =0. 2 2. Center the two thresholds optimal symmetric offset tolerance EECT 7326, Fall 2014 - 24 - Y. Chiu 12. 12/3/2014. The Architecture 3 decision levels ENOB = log23 = Max tolerance of comparator offset is VR/4. An implementation of the Sweeny-Robertson-Tocher (SRT) division principle The conversion accuracy relies on the loop-gain error, , the gain error and nonlinearity Vo = 2 Vi - b -1 VR A 3-level DAC is required Can the same technique be applied to SAR? Ref. [2]. EECT 7326, Fall 2014 - 25 - Y. Chiu Multiplier DAC (MDAC). C1 C2 C. Vo Vi b 1 2 VR Vo = 2 Vi - b -1 VR.

7 C1 C1. 2X gain + 3-level DAC + subtraction all integrated Can be generalized to architectures EECT 7326, Fall 2014 - 26 - Y. Chiu 13. 12/3/2014. Multiplier DAC (MDAC). 2. Vo 1 C1 VR. Vi b=0 b=1 b=2 b=3 b=4 b=5 b=6. 1 C2 VR/2. VR1. 1 C3 Vi VR6 0. 6 CMP's b 1 C4 -VR/2. A Vo -VR 2. 1e 2 -VR -5VR/8 -3VR/8 -VR/8 VR/8 3VR/8 5VR/8 VR. 0 Decoder 2. VR. Vo = 4 Vi - b - 3 VR. 4X gain + 7-level DAC + subtraction all integrated EECT 7326, Fall 2014 - 27 - Y. Chiu Residue Transfer Function ( MDAC). overflow range normal range underflow range Only half of the internal dynamic range is used under ideal condition! EECT 7326, Fall 2014 - 28 - Y. Chiu 14. 12/3/2014. With comparator offset overflow range normal range underflow range EECT 7326, Fall 2014 - 29 - Y. Chiu Internal Redundancy overflow range normal range underflow range Comparator and amplifier offsets tolerated by internal redundancy. EECT 7326, Fall 2014 - 30 - Y. Chiu 15. 12/3/2014. How does Redundancy work in SAR? Binary search is efficient, but displays zero error tolerance.

8 EECT 7326, Fall 2014 - 31 - Y. Chiu Binary Search Revisited +FS 1111. VX. 1110. 1101. 1/2 1100. 1. 1011. 1/4 3/8 1010. 1. 1001. Vin 0 1000. 0 0111. 0 1. 0110 0. 0101. 0100. 0011. 0010. 0001. 0000. -FS. t t When everything is ideal . EECT 7326, Fall 2014 - 32 - Y. Chiu 16. 12/3/2014. Binary Search w/ Dynamic Error +FS 1111. VX. 3/4 1110. 5/8 1101. 1/2 1100. 1. 1011. 1/4 3/8 1010. 1. 1001 1. Vin 0 1000. 0 0111. 0 1. 0110 0 0. 0101. 0100 0. 0011. 0010. 0001. 0000. -FS. t t Settling error, comparator hysteresis etc. EECT 7326, Fall 2014 - 33 - Y. Chiu Overlapping Search Ranges +FS 1111. VX. 1110. 1101. 1 1100. 0 1. 1 0 1 1011. 1010. 1001. 1 1. Vin 1000 0. 0 0111. 0. 0110. 0. 0101. 0100. 0011. 0010. 0001. 0000. -FS. t t Results indicate decision trajectory, no longer binary-coded. EECT 7326, Fall 2014 - 34 - Y. Chiu 17. 12/3/2014. Redundancy of Sub-binary Search +FS 1111. VX. 1110. 0 1101. 1 0 1 1100. 1. 1011. 1010. 1. 1. 1 0 1 1 1001. 1 1. Vin 1000 0. 0 1 0111. 0. 0 0. 0110. 0101. 0100.

9 0011. 0010. 0001. 0000. -FS. t t Dynamic errors absorbed by redundancy. EECT 7326, Fall 2014 - 35 - Y. Chiu SAR Redundancy Redundant conversion consumes more bit cycles, but can recover intermediate decision errors. Redundancy can be exploited to expedite conversion progress or to save power. DAC levels (matching) still need to be accurate. (will come back to this later ). EECT 7326, Fall 2014 - 36 - Y. Chiu 18. 12/3/2014. Presentation Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital -Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-ADC, sub-DAC, input). Two-ADC Equalization ( , split-ADC, ODC). Energy Efficiency and Trend Summary EECT 7326, Fall 2014 - 37 - Y. Chiu Pipelined ADC Errors (I). MDAC. Capacitor mismatch Op-amp finite-gain error and nonlinearity Charge injection and clock feed-through (S/H). Settling error Vo = 2 Vi - d VR. C1 C2 C2. Vo t f V d VR. C1 C2 S /H i C1 C2. C1 C1 . A Vo A Vo . EECT 7326, Fall 2014 - 38 - Y.

10 Chiu 19. 12/3/2014. Pipelined ADC Errors (II). MDAC. DAC bit-encoding scheme dj -3 -2 -1 0 1 2 3. dj,1 -1 -1 -1 -1 -1 0 1.. dj,2 -1 -1 -1 0 1 1 1. dj,3 -1 0 1 1 1 1 1. dj = dj,1 + dj,2 + dj,3. C C C3 C4 + C A Vj+1 . Vj = d j,1 1 + d j,2 2 + d j,3 Vr + Vj+1 . C C C C. EECT 7326, Fall 2014 - 39 - Y. Chiu RA Gain Error and Nonlinearity b=0 b=1 b=2. VR Do Vo VR/2. Vi 0. -VR/2. 0. -VR -VR/4 VR/4 VR -VR Vi VR. EECT 7326, Fall 2014 - 40 - Y. Chiu 20. 12/3/2014. RA Gain Error and Nonlinearity b=0 b=1 b=2. VR Do Vo VR/2. Vi 0. -VR/2. 0. -VR -VR/4 VR/4 VR -VR Vi VR. Raw accuracy is usually limited to 10-12 bits w/o error correction. EECT 7326, Fall 2014 - 41 - Y. Chiu RA Gain Error and Nonlinearity b=0 b=1 b=2. VR Do Vo VR/2. Vi 0. -VR/2. 0. -VR -VR/4 VR/4 VR -VR Vi VR. Raw accuracy is usually limited to 10-12 bits w/o error correction. EECT 7326, Fall 2014 - 42 - Y. Chiu 21. 12/3/2014. The Basic Idea of Digital Calibration Digital ADC. Computation Unknown System System Inversion Calibration = efficient Digital processing to undo certain analog errors , SC amplifier: Analog soln: match C1 and C2.