ARINC 429 Bus Interface - Actel

1 September 2006v 5 . 01 2006 Actel CorporationARINC 429 Bus Interface Product SummaryIntended Use ARINC 429 Transmitter (Tx) ARINC 429 Receiver (Rx)Key Features Supports ARINC Specification 429-16 Configurable up to 16 Rx and 16 Tx Channels Programmable FIFO Depth Up to 512 Words Programmable Interrupt Generation Rx and Tx Channels independently Up to 64 Words Configurable Label Memory Size Rx and Tx Channels independently Up to 256 Words Internal, Wrap-Around Testing Software Compatible with Legacy Devices Selectable Clock Speed 1, 10, 16, or 20 MHz Selectable Data Rate on Each Channel 100 kbps Optional 50 kbps CPU Interface Provides Direct CPU Access to Memory Simple Interface to Core8051 Memory EDAC Support with RTAX-S Family ARINC 429 Bus Interface Supports Standard line drivers and Receivers Available as Integrated Tx and RxSupported Families Fusion ProASIC 3/E ProASICPLUS Axcelerator RTAX-SCore Deliverables Evaluation Version Compiled RTL Simulation Model, Compliantwith the Actel Libero Integrated DesignEnvironment (IDE)

2 Netlist Version Structural VHDL and Verilog Netlists RTL version VHDL or Verilog Core Source Code Synthesis Scripts Verification Testbench Verilog User Testbenches Libero IDE Compatible VHDL and VerilogDevelopment System Complete ARINC 429 Rx/Tx Implementation Implemented in an APA600 Device Controlled Via an External Terminal UsingCore8051 and RS232 Links Includes line Driver and Receiver ComponentsSynthesis and Simulation Support Directly Supported within the Actel Libero IDE Synthesis: Synplicity ExemplarTM Synopsys Simulation Vital-Compliant VHDL Simulators OVI-Compliant Verilog SimulatorsVerification and Compliance Actel -Developed Simulation Testbench Core Implemented on the ARINC 429 Development SystemARINC 429 Bus DescriptionCore429 provides a complete Transmitter (Tx) andReceiver (Rx).

3 A typical system implementation usingCore429 is shown in Figure core consists of three main blocks: Transmit, Receive,and CPU Interface (Figure 1). Core429 requiresconnection to an external CPU. The CPU interfaceconfigures the transmit and receive control registers andinitializes the label memory. The core interfaces to theARINC 429 bus through an external ARINC 429 line driverand line receiver. A detailed description of the Rxinterface and Tx Interface is provided in the "FunctionalDescription" section on page ComponentsThere are two external components required for properoperation of Core429: Standard ARINC 429 line driver Standard ARINC 429 line receiverARINC 429 OverviewARINC 429 is a two-wire, point-to-point data bus that isapplication-specific for commercial and transportaircraft.

4 The connection wires are twisted pairs. Wordsare 32 bits in length and most messages consist of asingle data word. The specification defines the electricalstandard and data characteristics and protocols. ARINC 429 uses a unidirectional data bus standard (Txand Rx are on separate ports) known as the Mark 33 Digital Information Transfer System (DITS). Messages aretransmitted at , 50 (optional), or 100 kbps to othersystem elements that are monitoring the bus transmitter is always transmitting either 32-bit datawords or the Null state. The ARINC standard supports High, Low, and Null states(Figure 2). A minimum of four Null bits should betransmitted between ARINC words. No more than 20receivers can be connected to a single bus (wire pair) andno less than one receiver, though there will normally 3 on page 3 shows the bit positions of ARINC word contains five fields: ParityContentsGeneral Description.

5 2 ARINC 429 Overview .. 2 Core429 Device Requirements .. 3 Memory Requirements .. 4 Core429 Overview .. 5 Default Mode .. 5 Functional Description .. 5 Legacy Mode .. 7 Core Parameters .. 8I/O Signal Descriptions .. 8 Default Mode Operation .. 10 Legacy Operation .. 13 Status Register .. 15 CPU Interface Timing for Default Mode .. 16 Clock Requirements .. 17 Core429 Verification .. 17 Testbench .. 17 line drivers .. 18 line Receivers .. 18 Loopback Interface .. 18 Development System .. 18 Ordering Information .. 19 List of Changes .. 20 Datasheet Categories .. 21 Figure 1 Typical Core429 System One Tx and One RxFigure 2 ARINC StandardActel FPGACPUGlue LogicCoreARINC429Rx I/FTx I/FRxHiRxLoTxHiTxLoCPU Interface123456789103211111100000 BitNumber"A" Leg"B" LegDataABHighNullLow+50 5 HighNullLow+50 5 ARINC 429 Bus Sign/Status Matrix Data Source/Destination Identifiers LabelThe parity bit is bit 32 (the MSB).

6 SSM is the Sign/StatusMatrix and is included as bits 30 and 31. Bits 11 to 29contain the data. Binary Coded Decimal (BCD) and binaryencoding (BNR) are common ARINC data formats. Dataformats can also be mixed. Bits 9 and 10 are Source/Destination Identifiers (SDI) and indicate for whichreceiver the data is intended. Bits 1 to 8 contain a label(label words) identifying the data type. Label words are quite specific in ARINC 429. Each aircraftmay be equipped with different electronic equipmentand systems needing interconnection. A large amount ofequipment may be involved, depending on the ARINC specification identifies the equipment ID, aseries of digital identification numbers. Examples ofequipment are Flight Management Computers, InertialReference Systems, Fuel Tanks, Tire Pressure MonitoringSystems, and GPS Sensors.

7 Transmission OrderThe least significant bit of each byte, except the label, is transmitted first, and the label is transmitted ahead of thedata in each case. The order of the bits transmitted on the ARINC bus is as follows:8, 7, 6, 5, 4, 3, 2, 1, 9, 10, 11, 12, 13 .. Device RequirementsCore429 can be implemented in several Actel FPGA devices. Table 1 through Table 5 on page 4 provide typicalutilization figures using standard synthesis tools for different Core429 configurations. Table 1 assumes that the labelsize is set to 64 and FIFO depth is set to 64. Figure 3 ARINC Data Bit Positions323111109 LABEL302918 LSBDATA PADDISCRETESSDIPSSMMSBTa b l e 1 Device Utilization for One Tx ModuleCells or TilesFamilyCombinatorialSequentialTotalM emory BlocksDeviceUtilizationFusion3631475101 AFS6004%ProASIC3/E3631475101A3PE6004%Pro ASICPLUS4411465871 APA07519%Axcelerator2121453571AX12518%RT AX-S2581714291 RTAX250S10%Ta b l e 2 Device Utilization for One Rx ModuleCells or TilesFamilyCombinatorialSequentialTotalM emory BlocksDevicesUtilizationFusion4312336642 AFS6005%ProASIC3/E4312336642A3PE6005%Pro ASICPLUS5882368242 APA07527%Axcelerator3072345412AX12527%RT AX-S3502596092 RTAX250S14% ARINC 429 Bus clock rate can be programmed to be 1, 10, 16, or20 MHz.

8 All the Actel families listed above easily meetthe required I/O requirements depend on the systemrequirements and the external interfaces. If the core andmemory blocks are implemented within the FPGA andthe CPU Interface has a bidirectional data bus, thenapproximately 74 I/O pins are required to implementfour Rx and four Tx modules. The core will require 62pins to implement one Rx and one Tx core has various FIFO flags available for debuggingpurposes. These flags may not be needed in the finaldesign and this will reduce the I/O RequirementsThe number of memory blocks required differs, depending on whether each channel is configured the same Channel Configured the SameUse EQ 1 to calculate the number of memory blocks required if each channel is configured the of memory blocks = NRx * (INT (LABEL_SIZE/X) + INT (RX_FIFO_DEPTH/Y) + NTx * INT (FIFO_DEPTH/Y))

9 ,EQ 1Ta b l e 3 Device Utilization for One Rx and One Tx ModuleCells or TilesFamilyCombinatorialSequentialTotalM emory BlocksDeviceUtilizationFusion8486091,457 3 AFS60010%ProASIC3/E8486091,4573A3PE60010 %ProASICPLUS1,0843771,4613 APA07548%Axcelerator5183788963AX12544%RT AX-S6044291,0333 RTAX250S24%Ta b l e 4 Device Utilization for 16 Rx and 16 Tx ModulesCells or TilesFamilyCombinatorialSequentialTotalM emory BlocksDeviceUtilizationFusion13,4359,614 23,04948 AFS150060%ProASIC3/E13,4359,61423,04948A 3PE150060%ProASICPLUS16,8355,92822,76348 APA75069%Axcelerator8,0445,94413,98848AX 200043%RTAX-S9,5946,74516,33948 RTAX2000S51%Ta b l e 5 Device Utilization for Legacy Mode (2 Rx and 1 Tx)FamilyCells or TilesMemory BlocksDeviceUtilizationCombinationalSequ entialTotalFusion1,4441,0682,5125 AFS60018%ProASIC3/E1,4441,0682,5125A3PE6 0018%ProASICPLUS1,8406742,5145 APA15041%Axcelerator9556531,6085 RTAX250S20%RTAX-S1,0627291,7915 RTAX250S42% ARINC 429 Bus NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round upto the next integer, and X and Y are defined in Table Channel Configured DifferentlyUse EQ 2 to calculate the number of memory blocks required if each channel is configured of memory blocks = INT(FIFO_DEPTH[I]/Y + (INT(LABEL_SIZE[I]/X) + INT(FIFO_DEPTH[I]/Y)))

10 ,EQ 2where NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round upto the next integer, and X and Y are defined in Table for the ProASIC3/E Device FamilyIf the design has 2 receivers, 1 transmitter, 64 labels for each receiver, 32-words-deep FIFO for each receiver andtransmitter, then the number of memory blocks = 2 * (INT (64/512) + INT (32/128)) + 1 * INT (32/128) = 2 * (1 + 1) + 1 * (1) = the design has 2 receivers, 1 transmitter, 32 labels for receiver # 1, 64 labels for receiver # 2, 32 words-deep FIFO forreceiver # 1, 64-words-deep FIFO for receiver # 2, and 64-words-deep FIFO for transmitter, then the number of memory blocks = INT (64/128) + (INT (32/512) + INT (32/128)) + (INT (64/512) + INT (64/128)) = 1 + (1 + 1) + (1 + 1) = OverviewCore429 provides a complete and flexible Interface to amicroprocessor and an ARINC 429 data bus.