Build, Run, and Write RISC-V Programs

1 Build, Run, and Write RISC-V ProgramsCS250 Tutorial 3 (Version 091110b)September 11, 2010 Yunsup LeeIn this tutorial you will gain experience using the RISC-V toolchain to assemble and compileprograms for the RISC-V v2 processor which you will implement in lab 2 and 3. You will also learnhow to run the Programs on the RISC-V ISA simulator and use the test macros to Write your owntest RISC-V toolchain is a standard GNU cross compiler toolchain ported for RISC-V . You willbe usingriscv-{gcc,as,ld}to compile, assemble, and link your source files. Then you willrun the compiled binary on the RISC-V ISA simulator to figure out whether your binary runsas intended. The RISC-V ISA simulator might report errors because of the RISC-V compilergenerating instructions that are not defined in the RISC-V ISA. You need to carefully Write Ccode to avoid these instructions. Please referRISC-V Processor Specificationfor more informationabout the ISA.

2 You will use the same binary for the test harness used in lab 2 and 3. For debuggingpurposes, you can also compile benchmarks written in C natively, and run the binary on the hostx86 1 shows how everything fits VCS SIMVPDTestOutputsDVE GUICS ourceCodegccHostBinaryExecute Binaryfesvr -testrunTestOutputsTestOutputsFigure 1: RISC-V Assembler and Compiler ToolchainCS250 Tutorial 3 (Version 091110b), Fall 20102 Getting startedYou can follow along through the tutorial yourself by typing in the commands marked with a % symbol at the shell prompt. To cut and paste commands from this tutorial into your bash shell (and make sure bash ignores the % character) just use an alias to undefine the % characterlike this:% alias %=""All of the CS250 tutorials should be ran on an EECS Instructional machine. Please see the coursewebsite for more information on the computing resources available for CS250 students. Once youhave logged into an EECS Instructional you will need to setup the CS250 toolflow with the source ~cs250/ begin this tutorial you will need to copy RISC-V test assembly source files and C benchmarksource files from the course mkdir tut3% cd tut3% TUTROOT=$PWD% cp -R ~cs250/riscv-tests/ $TUTROOT% cp -R ~cs250/riscv-bmarks/ $TUTROOTB uilding RISC-V Test Assembly ProgramsYou will begin by assembling test program.

3 Take a look at theassembly inriscv- notice that this test only has two can use the following commands to generate a binary file, and an assembly dump cd $TUTROOT/riscv-tests% riscv-gcc -O2 -G 0 -nostdlib -nostartfiles -T \ -o riscv-v1_simple% riscv-objdump --disassemble-all --disassemble-zeroes \--section=.text --section=.data riscv-v1_simple > the to the Usinga combination of the assembly file and the objdump file you can get a good feel for what the testprograms are supposed to do and what instructions are supposed to be can use the makefile to automate the process of building RISC-V test assembly Programs . Thefollowing commands will clean the build directory and then build the binary rm -f riscv-v1_simple make that the corresponding RISC-V binary and objdump file were program is located locally in thetut3/riscv-testsdirectory. Globallyinstalled RISC-V assembly test Programs are located in~cs250/install/riscv-testswhich youcan use for lab 2 and 3 and projects.

4 The following command will build all of the assembly Tutorial 3 (Version 091110b), Fall 20103% makeRunning RISC-V Test Assembly Programs on the ISA SimulatorNow run your compiled RISC-V binary on the RISC-V ISA cd $TUTROOT/riscv-tests% fesvr -testrun riscv-v1_simple** PASSED **In order to see more detailed trace of the run, you can use the interactive mode with a d cd $TUTROOT/riscv-tests% fesvr -testrun -d riscv-v1_simple:<enter>core 0: 0x0000000000000000 (0xec100001) move v0,v0:<enter>core 0: 0x0000000000000004 (0xfc185000) mtpcr v0,$cr16:** PASSED **% fesvr -testrun -d riscv-v1_simple:while tohost 0 0** PASSED **% fesvr -testrun -d riscv-v1_simple:<enter>core 0: 0x0000000000000000 (0xec100001) move v0,v0:reg 0 00x0000000000000000:mem 00xfc185000ec100001:while tohost 0 0:** PASSED **You can see the cycle count, pc, instruction, register dump, memory dump, and the disassembledinstruction. The first register of the instructionmtpcrtells you whether or not the test passed ornot.

5 Number 1 is used to indicate that the test passed, while the number bigger than 1 pointsyou to the failed testcase number. You can also use the automated makefile to run through all cd $TUTROOT/riscv-tests% make [ PASSED ] [ PASSED ] [ PASSED ] [ PASSED ] [ PASSED ] [ PASSED ] [ PASSED ] Tutorial 3 (Version 091110b), Fall 20104[ PASSED ] [ PASSED ] RISC-V Test Assembly ProgramsTake a look You can see helper macros which are used in various test assemblyprograms. Brief explanation of each macro follows. TESTRISCVBEGIN- This macro defines things that need to be included at the beginning ofthe test. TESTRISCVEND- This macro defines things that need to be included at the end of the test. TESTCASE(testnum,testreg,correctval, )-This macro defines a test case. Runsthecode, and loadstestnumto register$x28. Then checks if the value oftestregiscorrectval. If not, the program will jump tofailwhich is defined inTESTPASSFAIL.

6 TESTINSERTNOPS[0-10]-This macro definesnops. The number in macro the indicatesthe number ofnopsto be inserted. TESTIMMOP(testnum,inst,result,val1,imm)- Basic test for immediate instructions. Loadsval1to$x1, executesinst $x3,$x1,immand checks if theresultand$x3match. TESTIMMSRC1 EQDEST(testnum,inst,result,val1,imm)-Sim ilar test toTESTIMMOP, though,executesinst $x1,$x1,immand checks if theresultand$x1match. TESTIMMDESTBYPASS(testnum,nopcycles,inst ,result,val1,imm)-Destination regis-ter bypass test for immediate instructions. Loadsval1to$x1, executesinst $x3,$x1,immthen reads$x3from the next instruction which is separated bynopcycles. TESTIMMSRC1 BYPASS(testnum,nopcycles,inst,result,val 1,imm)-Source register by-pass test for immediate instructions. Loadsval1to$x1, waits fornopcycles, then executesthe instruction, and checks. TESTRROP(testnum,inst,result,val1,val2)- Basic test for register register $x1,val2to$x2, executesinst $x3,$x1,$x2and checks if theresultand$x3match.

7 TESTRRSRC1 EQDEST(testnum,inst,result,val1,val2)-Si milar test toTESTRROP, though,executesinst $x1,$x1,$x2and checks if theresultand$x1match. TESTRRSRC2 EQDEST(testnum,inst,result,val1,val2)-Si milar test toTESTRROP, though,executesinst $x2,$x1,$x2and checks if theresultand$x2match. TESTRRSRC12 EQDEST(testnum,inst,result,val1)-Similar test toTESTRROP, though,loadsval1to$x1, executesinst $x1,$x1,$x1and checks if theresultand$x1match. TESTRRDESTBYPASS(testnum,nopcycles,inst, result,val1,val2)-Destination regis-ter bypass test for register register instructions. Loadsval1to$x1,val2to$x2, executesinst$x3,$x1,$x2then reads$x3from the next instruction which is separated bynopcycles. TESTRRSRC12 BYPASS(testnum,src1nops,src2nops,inst,re sult,val1,val2)-Sourceregister bypass test for register register instructions. Loadsval1to$x1, waitssrc1nops,loadsval2to$x2, waitssrc2nops, then executes instruction, and checks. TESTRRSRC21 BYPASS(testnum,srcnops,src2nops,inst,res ult,val1,val2)-Similar toTESTRRSRC12 BYPASS, though, loadsval2to$x2before loadingval1to$ Tutorial 3 (Version 091110b), Fall 20105 TESTLDOP(testnum,inst,result,offset,base )-Basic test for load instructions.

8 Loadsbaseto$x1, executesinst $x3,offset($x1)and checks if theresultand$x3match. TESTSTOP(testnum,loadinst,storeinst,resu lt,offset,base)-Basic test for store in-structions. Loadsbaseto$x1,resultto$x2, executesstoreinst $x2,offset($x1)andloadinst $x3,offset($x1)and checks if theresultand$x3match. TESTLDDESTBYPASS(testnum,nopcycles,inst, result,offset,base)-Destination reg-ister bypass test for load instructions. Loadsbaseto$x1, executesinst $x3,offset($x1),then reads$x3from the next instruction which is separated bynopcycles. TESTLDSRC1 BYPASS(testnum,nopcycles,inst,result,off set,base)-Source register by-pass test for load instructions. Loadsbaseto$x1, waitsnopcycles, then executes instruc-tion, and checks. TESTSTSRC12 BYPASS(testnum,src1nops,src2nops,loadins t,storeinst,results,offset,base)-Source register bypass test for store instructions. Loadsresultto$x1, waits forsrc1nops,loadsbaseto$x2, waits forsrc2nops, executes thestoreinstructionand theloadinstruction,then checks if theresultand$x3match, TESTSTSRC21 BYPASS(testnum,src1nops,src2nops,loadins t,storeinst,results,offset,base)-Similar toTESTSTSRC12 BYPASS, though, loadsbaseto$x2before loadingresultto$x1.

9 TESTBR1 OPTAKEN(testnum,inst,val1)-Basic taken test for branch instructions with oneinput. Loadsval1to$x1, then executesinst $x1,pass. If branch is not-taken the programwill jump tofailwhich is defined inTESTPASSFAIL. TESTBR1 OPNOTTAKEN(testnum,inst,val1)-Basic not-taken test for branch instructionswith one input. Loadsval1to$x1, then executesinst $x1,fail. If branch is taken theprogram will jump tofailwhich is defined inTESTPASSFAIL. TESTBR1 SRC1 BYPASS(testnum,nopcycles,inst,val1)-Sour ce register bypass test forbranch instructions with one input. Loadsval1to$x1, waits fornopcycles, then executesbranch instruction. TESTBR2 OPTAKEN(testnum,inst,val1,val2)-Basic taken test for branch instruction withtwo inputs. Loadsval1to$x1,val2to$x2, then executesinst $x1,$x2,pass. If branchis not-taken the program will jump tofailwhich is defined inTESTPASSFAIL. TESTBR2 OPNOTTAKEN(testnum,inst,val1,val2)-Basic not-taken test for branch instruc-tion with two inputs.

10 Loadsval1to$x1,val2to$x2, then executesinst $x1,$x2, branch is taken the program will jump tofailwhich is defined inTESTPASSFAIL. TESTBR2 SRC12 BYPASS(testnum,src1nops,src2nops,inst,va l1,val2)-Source registerbypass test for branch instruction with two inputs. Loadsval1to$x1, waits forsrc1nops,loadsval2to$x2, waits forsrc2nops, executes branch instruction. TESTBR2 SRC21 BYPASS(testnum,src1nops,src2nops,inst,va l1,val2)-This macro issimilar toTESTBR2 SRC12 BYPASS, though, loadsval2to$x2before loadingval1to$x1. TESTJRSRC1 BYPASS(testnum,nopcycles,inst)-Loads an address to$x6, waits fornopcycles,then executes jump register instruction. TESTJALRSRC1 BYPASS(testnum,nopcycles,inst)-Similar toTESTJRSRC1 BYPASS, though,executes jump and link register instruction. TESTPASSFAIL- This macro defines what do to when success or fail. RISC-V v2 defines thismacro usingmtpcr. SETSTATS(enable)-This macro stimulates the test harness to turn logging $TUTROOT/riscv- see how the macros are Tutorial 3 (Version 091110b), Fall 20106#include " "TEST_RISCV_BEGINSET_STATS(1)#---------- ---------------------------------------- -----------# Arithmetic tests#---------------------------------- ---------------------------TEST_RR_OP( 2, addu, 0x00000000, 0x00000000, 0x00000000 );TEST_RR_OP( 3, addu, 0x00000002, 0x00000001, 0x00000001 );TEST_RR_OP( 4, addu, 0x0000000a, 0x00000003, 0x00000007 );TEST_RR_OP( 5, addu, 0xffff8000, 0x00000000, 0xffff8000 );TEST_RR_OP( 6, addu, 0x80000000, 0x80000000, 0x00000000 );TEST_RR_OP( 7, addu, 0x7fff8000, 0x80000000, 0xffff8000 );TEST_RR_OP( 8, addu, 0x00007fff, 0x00000000, 0x00007fff );TEST_RR_OP( 9, addu, 0x7fffffff, 0x7fffffff, 0x00000000 );TEST_RR_OP( 10, addu, 0x80007ffe, 0x7fffffff, 0x00007fff );TEST_RR_OP( 11, addu, 0x80007fff, 0x80000000, 0x00007fff ).