EE105 –Fall 2015 Microelectronic Devices and Circuits

1 EE105 fall 2015 Microelectronic Devices and CircuitsMulti- Stage AmplifiersProf. Ming C. Wu Sutardja Dai Hall (SDH)Terminal Gain and I/O Resistances of MOS AmplifiersAV,t= gmRL1+gmRSRi= Ro=ro1+gmRE()#$%&AI,t= Without dege ne ration:Simpl y set RS=0AV,t=RL1gm+RLRi= Ro=1gmAI,t= AV,t=gmRLRi=1gmRo=ro1+gmRE()!"#$AI,t 1 For the gain, Ri, Roof the whole amplifier, you need to include voltage/current dividers at input and output stagesCommon Source(CS)Common Drain (CD)Common Gate (CG)Summary of MOS single - Transistor AmplifiersMOSC ommon SourceCommon Sourcewith DrainCommon GateRi SmallRoLargeVery LargeSmallLargeAVModerateSmall~ 1 ModeratefHSmallModerateLargeLargeSingle Stage Amplifier Cannot Meet All Requirements For example, a general purpose operational amplifier requires High input resistance ~ 1M Low output resistance ~ 100 High voltage gain ~ 100,000 No single transistor amplifier can satisfy all spec s Cascading multiple stages of amplifiers offers a path towards the designMultistage Amplifiers Usually An input stage to provide required input resistance Middle stage(s)

2 To provide gain An output stage to provide required output resistance or drive external loads More gain ! Gain/stage limited, especially in nanoscale Devices Improve Bandwidth De- couple high impedance nodes from large capacitors DC coupling (no passive elements to block the signal) Use amplifiers to naturally level shift signalImpedance Match On - chip Circuits often use voltage/current matching to minimize loading Keep in mind the input resistance and output resistance of each type of stage so that the loading does not create an undesired effect IdealRinIdealRoutVoltage Amplifier 0 Current Amplifier0 TransconductanceAmplifier TransresistanceAmplifier00 Two - Stage Voltage Amplifier Boost gain by cascading Common- Source stagesCS1CS2 Can combine into a single 2- port modelResults of new 2- port: Rin= Rin1,Rout= Rout2CS1,2CS Cascade Analysisvinvoutgm1vingm2vintvintResults of new 2- port.

3 Rin= Rin1= Rout= Rout2=AV= vout/vin= CS Cascade Bandwidthvinvoutgm1vingm2vintvintTwo time constants: 1= 2=Bandwidth Extension Common Source stage has high gain, but low bandwidth Note that Miller effect is the culprit Follower stage can buffer source resistance from Miller capBandwidth Extension Using Source Follower (SF)vingm1vinvintvoutgm2vintCOMMON SOURCECOMMON DRAINCOMMON SOURCE CS Example with Cap Load Cinand CSare very large, therefore they look like short Circuits to the AC signal. If CLis very large, its pole dominates, let s analyzeCS with Cap Load Small SignalRd What are the time constants associated with the capacitors in this circuit ?

4 What can we do if we have to drive a large CL?R2//Rg1//Rg2~R2CS with Cap Load Bandwidth How can we reduce the impact of CL? One way is to reduce the resistance Rd, but this reduces our low - frequency gain To recover the gain we can increase gm1. What does this cost us?CS with Cap Load BW Extension A better way to extend the bandwidth is to add a source- follower stage. Similar to previous exampleCS with Cap Load BW Extensionvingm1vinvint By adding a CD (Source Follower) we can increase the bandwidth It costs us power for the CD stage Remember that increasing the BW by increasing gm1costs us much morevint1/gm2CS + CG Common source provides gain, CG acts as a buffer, but is it even helping?

5 How do you bias this circuit ?Merged CS + CG = Cascode Let s apply 2- port small- signal analysis In this case, we care about the input current to the second stage Note that the input resistance of the CG is low, therefore the majority of the CS current is fed to the CG Av =vintvoutCascode Bandwidth Draw in the Cgsand Cgdcapacitors. Which ones are Miller effected? Is this better or worse than a CS without a CG?Cascode Bandwidth Draw in the capacitors and input resistancevintvoutCascode Biasingl CG has a very large output resistancel Loading it with RDis likely to reduce the voltage gainl We can increase the gain by using a current source load, but rocneeds to be very large.

6 Can use a cascode current mirror!Complete Amplifier DesignGoals: gm1= 1 mS, Rout=5 MW W For simplicity, let s assume all gmand rovalues are equalAV gm1 Rout= 1mS*5M = 5,000 Rout 12gmro2=5M ro=20M gm=10M 1mS=100k Bias Current & Device Sizingro=1 IDS=100k IDS= 1*100k =100 Agm=2k'WL IDS=1mSWL=gm22k'IDS=(1mS)22*100 *100 A=50 Need to know process parameters to solve for W/Lk = 100 A/V2 = [V- 1]Output (Voltage) SwingMaximum VOUT=Minimum VOUT=Input Bias VIN= Need to know VGS VT ( VDSAT , VOV)gm=2 IDSVGS VT=1mSVGS VT=2 IDSgm=2*100 A1mS=