1 1. Cabot Microelectronics Corporation Consumable Technologies to Cover a Wide Variety of CMP Applications US CMPUG, 9 April 2008. Presenter: Paul Feeney, Feeney CMP Fellow 2. Outline Need for new IC CMP applications Existing applications Tungsten, g , Dielectric,, Copper, pp , Barrier New applications Emerging IC. C applications Extension beyond IC's Summary 2008 Cabot Microelectronics Corporation 3. Why Do We Need New CMP Applications? New CMP applications arise when continuous improvement of consumables and equipment are not sufficient New applications are driven by smaller dimensions Requirements for a given CMP process get tougher Step function in performance needed Need to optimize away from general purpose consumables IC integration changes with each new advanced node New N andd more complexl structures t t d drive i new combinations bi ti off existing materials Increased complexity leads to segmentation of requirements New materials required to get
2 Chip performance and yield Benefits of CMP spilled over into DRAM and NVRAM/flash Accelerated A l t db by performance f 2008 Cabot Microelectronics Corporation requirements i t and d ffalling lli CMP C. CoO. O. 4. ITRS 2007 planarization Applications Fi t Y. First Year off IC Production P d ti 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022. DRAM 1/2 Pitch 65nm 57nm 50nm 45nm 40nm 35nm 32nm 28nm 25nm 22nm 20nm 18nm 16nm 14nm 13nm 12nm MAJOR APPLICATIONS. Dielectrics Sh ll Shallow ttrench h iisolation l ti (STI).
3 [direct]. Premetal dielectric (PMD). [target & selective]. Interlevel dielectric (ILD). [memory]. New applications [ Si nitride]. Conductors Polysilicon [selective & target]. Tungsten/buff [contact & via]. Copper/barrier [ > eff > ]. Copper/new barrier [ > eff > ]. Copper/new barrier [ > eff > ]. pp New applications [ new contact]. This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Research Required Development Underway Qualification / Pre-Production Continuous Improvement 2008 Cabot Microelectronics Corporation 5.
4 ITRS 2007 planarization Consumables First Year of IC Production 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022. DRAM 1/2 Pitch 65nm 57nm 50nm 45nm 40nm 35nm 32nm 28nm 25nm 22nm 20nm 18nm 16nm 14nm 13nm 12nm CONSUMABLES. Fluids High solids slurries Slurries with low solids/defects/cost Optimized formulations from tunable platforms Fluids for chemical enhanced planarization and ECMP. General cleaning solutions Cleaning and buff solutions tailored to applications Pads Urethane pads for new applications Abrasive containing pads Range of alternative pads for planarity/defects/cost This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.
5 Research Required Development Underway Qualification / Pre-Production Continuous Improvement 2008 Cabot Microelectronics Corporation 6. Core Product Pipeline Advanced Solutions Across Applications Advanced CMP Emerging Tungsten Dielectric / ILD Copper Barrier Pads Materials uct Evoluttion W2000 Semi-Sperse C5000 B5200 D100 Aluminum Series Series Series Series Ruthenium W6000 D1300 C6000. Series Series B6618 Nitride Series Produ W7000 D3500/D4500 C7000 B7000 Dielectric Series Series Series Series Poly D6700 C8000 B8500. Series Series Series Noble Metals D8100 Metal Gates Series 2008 Cabot Microelectronics Corporation 7.
6 Tungsten Solutions for Advanced Technologies X = Benchmark W2000. 2008 Cabot Microelectronics Corporation 8. Edge-Over-Erosion (EOE) Performance AMAT. Mirra 300 mm EOE is significantly reduced / eliminated with our advanced WIN . WIN products 2008 Cabot Microelectronics Corporation 9. Best-in-Class Defect Performance 2008 Cabot Microelectronics Corporation 10. W7300 Best-in-Class Performance Buff Step 1st Step: W2000 1:1 dil 700 605. 600 520 Plug Device 500 um/25% density 400. 300. 200. 70. 100. 29 Erosion ( ). 0 16. 5 Microscratches Buff polish time Significant reduction in both defectivity and erosion after W7300 buff step 2008 Cabot Microelectronics Corporation 11.
7 WIN W7300 B21 / Epic D100 Combo Erosion Performance Mirra 200mm WBApps117: Patterned Plug Oxide Erosion D100 vs IC1000 for WIN W7300-B21 on Ebara 400. IC1000 Pad 200 nm Via, 350. 25% pattern density D100 Pad 300. Oxide Errosion ( /min)). 250. 200 Polish Process BSP = 225 hPa 150 SCP = 275 hPa RRP = 225 hPa CS = 55 rpm 100 SFR = 150 ml/min Polish time = 60 s 50 PS ((IC1000)) = 100 rpm p PS (D100) = 125 rpm 0. 0 5 10 15 20 25 30 35 40 45 50 55. Overpolish Time (s). 2008 Cabot Microelectronics Corporation 12. D100 Improved Defectivity Defect and Scratch Counts (MIT 854 Mask Patterned Wafers).
8 500. 400. otal Defects 300 Avg Scratch Count 18. Average Scratch Count 18. To 200. Average Scratch Count Avg Scratch 28 Count 28. 100. D100 Baseline Con. hard Pad pad > 35% de defectivity ect ty reduction educt o by us using g D100. 00 pads 2008 Cabot Microelectronics Corporation 13. D100 Longer Pad Life 6000 Longer pad life confirmed Epic D100 pad life, life 3. in high volume 5000. W Removal Ratte (A/min). HVM SimulationCoO Benefit manufacturing Con. hard pad from D100 pad 4000 end of life conventional hard pad 3000. 4x polyurethane impregnated polyester pad 2000.
9 1000 Improved CoO for Customers 0. 45. 45. 45. 45. 45. 45. 45. 45. 45. 45. 45. 25. 33. 45. 5. 5. 5. 34. 64. 94. 12. 15. 18. 21. 24. 27. 30. 33. 36. 39. 42. Wafer Run Number ** 15 mils groove depth 2008 Cabot Microelectronics Corporation 14. iDIEL D6720. and Extension to STI Applications D6720 D6720-B10. Ab i Type Abrasive T Hydrothermal Ceria none pH ~ Self-Stopping Additive Chemistry High Purity (no KOH). (SSA). Rate Control Additive Balanced Chemical Self-Stopping Mechanism & Mechanical When Added to C2. high Ox/SiN selectivity Mean Particle Size ~ 90 nm none Particle Concentration < none (POU).
10 2X Concentrated POU Mixing Method of Use POU or In-line mixing With D6720. with B10 or by itself 2008 Cabot Microelectronics Corporation 15. iDIEL D6720. Dielectric Removal on ILD Pattern SS25E-70% Stack D6720-70% Stack Thickness Planarity Target (SH + ~1500A). Normalized 8,000A. N. 20,000A. >30% Reduction in Polish Time 0 20 40 60 80 100 120 140 160. Polishing Time( sec). D6720 planarizes faster compared to SS25E (polishing time can be shorter). 2008 Cabot Microelectronics Corporation 16. iDIEL D6720. Defectivity on TEOS (Post HF Data).