CD4046B Phase-Locked Loop: A Versatile Building Block for ...

1 Application ReportSCHA002A - February 20031CD4046B Phase-Locked Loop: A Versatile BuildingBlock for micropower Digital and Analog ApplicationsDavid K. MorganStandard Linear & LogicABSTRACTA pplications of the CD4046B Phase-Locked loop device, such as FM demodulation, FSKdemodulation, tone decoding, frequency multiplication, signal conditioning, clocksynchronization, and frequency synthesis, are discussed. The monolithic-formlow-power-consumption CD4046B particularly is desirable for use in portablebattery-powered .. 2 Review of PLL Fundamentals3.. 3CD4046B PLL Technical Description4.. Phase Comparators5.. Voltage-Controlled Oscillator (VCO)11.

2 CD4046B PLL Performance Summary12.. 4CD4046B PLL Applications17.. FM Demodulation17.. Frequency Synthesizer19.. Split-Phase Data Synchronization and Decoding20.. PLL Lock Detection21.. SCHA002A2CD4046B Phase-Locked Loop: A Versatile Building Block for micropower Digital and Analog ApplicationsList of Figures1 PLL Block Diagram3.. 2 CD4046B PLL Block Diagram4.. 3 CD4046B PLL Phase Comparator Section Schematic5.. 4 Phase Comparator I Characteristics at LPF Output6.. 5 Typical Waveforms for CD4046B PLL Employing Phase Comparator I in Locked Condition of fo7.. 6 Typical Waveforms for CD4046B PLL Employing Phase Caparator II in Locked Condition8.. 7 Phase Comparator II State Diagram9.

3 8 CD4046B VCO Section Schematic11.. 9 Component-Selection Criteria16.. 10 FM Demodulator17.. 11 FM Demodulator Voltage Waveforms18.. 12 Low-Frequency Synthesizer with Three-Decade Programmable Divider19.. 13 Frequency-Synthesizer Waveforms20.. 14 Split-Phase Data Synchronization and Decoding21.. 15 Lock-Detection Circuit22.. 16 Lock-Detection-Circuit Waveforms23.. List of Tables1 Maximum Ratings and General Operating Characteristics13.. 2 VCO Electrical Characteristics13.. 3 Comparator Electrical Characteristics14.. 4 Phase Comparator Comparison15.. SCHA002A3 CD4046B Phase-Locked Loop: A Versatile Building Block for micropower Digital and Analog Applications1 IntroductionPhase-locked loops (PLLs), especially in monolithic form, have significantly increased use insignal-processing and digital systems.

4 Frequency modulation (FM) demodulation, frequencyshift keying (FSK) demodulation, tone decoding, frequency multiplication, signal conditioning,clock synchronization, and frequency synthesis are some of the many applications of a PLL. ThePLL described in this application report is the CD4046B , which consumes only 600 W of powerat 10 kHz, a reduction in power consumption of 160 times when compared to the 100 mWrequired by similar monolithic bipolar PLLs. This power reduction has particular significance forportable battery-operated equipment. This application report discusses the basic fundamentalsof PLLs, and presents a detailed technical description of the CD4046B , as well as some of of PLL FundamentalsThe basic PLL system is shown in Figure 1.

5 The system consists of three parts: phasecomparator, low-pass filter (LPF), and voltage-controlled oscillator (VCO). All parts areconnected to form a closed-loop frequency-feedback (t)VO(t)foVe(t)Vd(t)VCO ControlVoltageComparatorInputComparatorI nputLPFVCOF igure 1. PLL Block DiagramWith no signal input applied to the PLL system, the error voltage at the output of the phasecomparator is zero. The voltage, Vd(t), from the LPF also is zero, which causes the VCO tooperate at a set frequency, fo, called the center frequency. When an input signal is applied to thePLL, the phase comparator compares the phase and frequency of the signal input with the VCOfrequency and generates an error voltage proportional to the phase and frequency difference ofthe input signal and the VCO.

6 The error voltage, Ve(t), is filtered and applied to the control inputof the VCO. Vd(t) varies in a direction that reduces the frequency difference between the VCOand signal-input frequency. When the input frequency is sufficiently close to the VCO frequency,the closed-loop nature of the PLL forces the VCO to lock in frequency with the signal input; ,when the PLL is in lock, the VCO frequency is identical to the signal input, except for a finitephase difference. The range of frequencies over which the PLL can maintain this lockedcondition is defined as the lock range of the system. The lock range always is larger than theband of frequencies over which the PLL can acquire a locked condition with the signal latter band of frequencies is defined as the capture range of the PLL Phase-Locked Loop: A Versatile Building Block for micropower Digital and Analog Applications3CD4046B PLL Technical DescriptionFigure 2 shows a Block diagram of the CD4046B , which has been implemented on a singlemonolithic integrated circuit.

7 The PLL structure consists of a low-power, linear VCO and twodifferent phase comparators, having a common signal-input amplifier and a common comparatorinput. A Zener diode is provided for supply regulation, if necessary. The VCO can beconnected either directly or through frequency dividers to the comparator input of the phasecomparators. The LPF is implemented through external parts because of the radicalconfiguration changes from application to application and because some of the componentscannot be integrated. The CD4046B is available in 16-lead ceramic dual-in-line packages (D andF suffixes), 16-lead dual-in-line plastic packages (E suffix), 16-lead small outline package (NSRsuffix) and in chip form (H suffix).

8 Comparator InVCO OutPhaseComparator IIPhaseComparator IPhase Comparator I OutPhase Comparator II OutPhase PulsesVCO InDemodulator OutRSVSSVSSVSSZ enerVCOVSSVSSC1 Signal InVDDLPF(see Figure 10)SourceFollower NCD4046BR3C2R1R2 Inhibit12345678910111213141516 Figure 2. CD4046B Block DiagramSCHA002A5 CD4046B Phase-Locked Loop: A Versatile Building Block for micropower Digital and Analog ComparatorsMost PLL systems utilize a balanced mixer, composed of well-controlled analog amplifiers forthe phase-comparator section. The CD4046B design employs digital-type phase comparators(see Figure 3). Both phase comparators are driven by a common-input amplifier configurationcomposed of a bias stage and four inverting-amplifier stages.

9 The phase-comparator signalinput (terminal 14) can be direct coupled, provided the signal swing is within CMOS logic levels[logic 0 30% (VDD VSS), logic 1 70% (VDD VSS)]. For smaller input signal swings, the signalmust be capacitively coupled to the self-biasing amplifier at the signal input to ensure anoverdriven digital signal into the phase II OutPhase Pulses OutPhase Comparator IIPhase Comparator IComparator InputInput AmplifierQQQQS ignalInputPhase Comparator I OutVSSVDD1423 RRSQRSRRSQSR1pn13 Figure 3. CD4046B Phase-Comparator Section SchematicSCHA002A6CD4046B Phase-Locked Loop: A Versatile Building Block for micropower Digital and Analog ApplicationsPhase comparator I is an exclusive-OR network that operates analogously to an overdrivenbalanced mixer.

10 To maximize the lock range, the signal- and comparator-input frequencies musthave 50% duty cycle. With no signal or noise on the signal input, this phase comparator has anaverage output voltage equal to VDD/2. The LPF connected to the output of phase comparator Isupplies the averaged voltage to the VCO input and causes the VCO to oscillate at the centerfrequency (fo). With phase comparator I, the range of frequencies over which the PLL canacquire lock (capture range) is dependent on the LPF characteristics and can be made as largeas the lock comparator I enables a PLL system to remain in lock despite high amounts of noise in thesignal characteristic of this type of phase comparator is that it can lock onto input frequencies thatare close to harmonics of the VCO center frequency.