CMOS Capacitance and Circuit Delay

1 Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 CMOS Capacitance and Circuit DelayA) CMOS Structure and CapacitanceB) gate and Source Drain Capacitance ModelC) Cascade Inverter DelayD) Capacitance from Logic FunctionE) Fan-Out and Logic DelayReading: Schwarz and Oldham, pp. 518-526, and lectures 16-19. Lecture 24 Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Dynamic Performance: Add CapacitancesCapacitance CGis between gate and the underlying channel, which is connected to the source, CGS= CG and hence is modeled as Capacitance to LWCC= =LWArea of GateWCLWCC perimeterjunctionSD + =min4 Capacitance CSDhas a bottom and out-side perimeter between the source or drain and the underlying substrate which is connected to ground.

2 There is also a gate perimeter component for which there is a 2X magnifying (Miller) effect on the S/D side because the gate swings the opposite direction of the 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 gate Capacitance ModeloxoxoxGtWL LWCC= =()()27714 == =L = mW = m() = EE42 Simplified CGmodel:CG/MS= (ie. fF per Minimum Square of gate layout)Note: CGis proportional to (W/L)Example For Gates with the minimum length of m: (W/L)n= = has MS and has CG= fF.(W/L)p= = has MS and has CG= Constant for SiO2 Copyright 2001, Regents of University of CaliforniaEECS 42 Intro.

3 Electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Source/Drain Capacitance ModelExample: (W/L)n= , => with CSD= : (W/L)p= => with CG= + =min4 Accurately evaluating CSDinvolves modeling the advanced physics of junctions and is considered in somewhat more detail in EECS generally proportional to Simplified CGmodel:CSD= (ie. fF per Minimum m Feature length)Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 MODEL vout vin VDD Dn Sn Gn Rn CGn Dp Sp Gp CGp Rp vout vin VDD CDn CDp The CMOS Inverter with Parasitic capacitancesSymbolic circuitNote that the switches are NOT independent , in fact they are ganged ModelCopyright 2001, Regents of University of CaliforniaEECS 42 Intro.

4 Electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 gate - Delay Analysis -- Identify key Components12 Basic case: one inverter driving anothertVThen Vout1goes from low to high (but a little bit later .. delayed ). Of course Vin2is the same as Vout2goes from high to low (delayed even more from the input Vin1).Suppose Vin1goes from high to low. MP2 turns on and MN1turns +-VDDMN3MP2MP4vvvin1vout2vout1vin1vout1v out2 Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Cascaded CMOS InvertersThe output of stage 1 must charge the Source/Drain capacitances of the first stage and the gate capacitances of the second is CDnand CDpof the first stage and CGnand CGpof the second stage.

5 Vin1 VDDvoutLOGIC STAGE Nvout21=vin2 STAGE N +1 CLOADCLOAD= CDn + CDp+ CGn+ CGpNote that there are no resistors, capacitors, inductors in a CMOS Circuit -- there are onlyNMOS and PMOS 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Typical Capacitance Values:Consider m technology with a typical NMOS X m as pull-down and X pull-upCLOAD= CDn + CDp+ CGn+ CGpCLOAD= ( + + + )( ) = (9)( ) = STAGE Nvout21=vin2 STAGE N +1 vout21=vin2vout21=vin2 STAGE N +1 (W/L) ratiosCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 The Circuit symbolResistance Model for SwitchingGSDIDN ChIDSIDVDSVDD/2 VDDFrom IDS=CdV/dtwe have t= C V/ IDS= C VDD/ 2 IDSBut if we had an RC discharge t = so the effective resistance, RDN,= t VDD/( X 2 IDS) =.

6 72 VDD/ IDSE lectrical ModelDSGRDNDSDDDNIV43R So we useRDN(3/4)VDDC opyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Resistance Model for SwitchingElectrical ModelDSGRDN = = For the m technology with VDD= = = For Wn= mFor Wp= 0. 75 mCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Inverter Propagation Delay t = (10k )( ) = 25 psDischarge (pull-down)Discharge (pull-up) t = (12k )( ) = 30 psVOUTVDDVIN =VddCOUT= = VddRDCOUT= 2001, Regents of University of CaliforniaEECS 42 Intro.

7 Electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Computer Circuits Are and Order of Magnitude Slower Than a Simple Source/drain Capacitance of a Circuit increases roughly proportional to the number of input signals. The resistance from the output node to ground of VDD increases roughly proportional to the number of input time to charge the internal source/drain capacitances is theproduct of the Capacitance and resistance and roughly increases as the square of the number of input delivery of the output signal to more than one logic gate (Fan-Out) introduces further loading proportional to the 13 will give an exampleCopyright 2001, Regents of University of CaliforniaEECS 42 Intro.

8 Electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 CLOADE xample CMOS (12+6+3+ )( ) = 9 fF R = 2 RDP= 24k t= (24k )(9 fF )= 149 psFor comparison the inverter had a pull-up Delay of 30 psWorst case is a=1, c =0, and b changes 1 => 0 Lump all at this this page carefully as three starting point mistakes were 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Fanout12nFanout is always 1 (there is always a load) gate capacitances sum and are charged by the driver LOAD= CLOAD+ (FO - 1)((W/L)p+(W/L)n)(CG/MS)Fan-Out (FO) = n C LOAD= CLOAD+ (FO - 1)( + )( fF)One load device was in included in the initial estimate of minimum length 2001, Regents of University of CaliforniaEECS 42 Intro.

9 Electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 Coping with Power ConsumptionTube: 300V x 20 mA = 6 WBipolar Transistor: 5V x 20 mA = 200 mWNMOS Transistor: 5V x 200 A = 1 mWCMOS Transistors: 5V x 100 nA = POWERPSHORT- Circuit = (1/2) ISHORT-CIRCUITVDD 30-70fCLOCK= (1/2) (60 A) ( ) (109) = WPDYNAMIC= (1/2)(1/2) C VDD2fCLOCK= (1/2) (1/2)(10 fF) ( )2109 = WTrue of every gate !True for only active of the gates change stateOnly the L =>H takes energy from VDDC opyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 24: 11/28/01 NeureutherVersion Date 12/01/01 What Might You be Buying for Christmas 2010?

10 Today s Technology: Pentium IV, 42 million transistors, 40-60 Watts, L = mIntel s Statements in San Francisco Chronicle pp. E1, 11/26/01: We don t see any fundamental barrier (to Moore s Law of scaling).Introduced a Tera-Hertz transistor for the 30 GHz (2010 generation)There is a problem of leakage of energy even when the transistors are in the off position. Intel s new design stems the energy flow by using a different material for the existing insulator in one area of the transistor while adding another insulator on top of the silicon. We re betting our entire business on this. If Intel wins their bet in 2010 you can use your knowledge from EE 42 to explain to the sales person how this technology improvement claim the leakage is 10,000 times smaller.