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CMOS Manufacturing Process

Digital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOSM anufacturingProcessDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOS ProcessDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessA Modern cmos Processp-welln-wellp+p-epiSiO2 AlCupolyn+SiO2p+gate-oxideTungstenTiSi2 DualDual--Well TrenchWell Trench--Isolated cmos ProcessIsolated cmos ProcessDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCircuit Under DesignThis two-inverter circuit (of Figure in the text) will bemanufactured in a twin-well Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCircuit LayoutDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessThe Manufacturing ProcessFor a great tour through the Process and its different steps, a complete walk-through of the Process (64 steps), check theBook web-pageDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing Processoxidationopticalmaskprocessstepph otoresistcoatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotores

development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process. Digital Integrated Circuits Manufacturing Process EE141 Patterning of SiO2 Si-substrate Si-substrate Si-substrate (a) Silicon base material (b) After oxidation and deposition

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Transcription of CMOS Manufacturing Process

1 Digital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOSM anufacturingProcessDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOS ProcessDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessA Modern cmos Processp-welln-wellp+p-epiSiO2 AlCupolyn+SiO2p+gate-oxideTungstenTiSi2 DualDual--Well TrenchWell Trench--Isolated cmos ProcessIsolated cmos ProcessDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCircuit Under DesignThis two-inverter circuit (of Figure in the text) will bemanufactured in a twin-well Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCircuit LayoutDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessThe Manufacturing ProcessFor a great tour through the Process and its different steps, a complete walk-through of the Process (64 steps), check theBook web-pageDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing Processoxidationopticalmaskprocessstepph otoresistcoatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotoresist stepper exposuredevelopmentTypical operations in a single photolithographic cycle (from [Fullman]).

2 Photo-Lithographic ProcessDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessPatterning of SiO2Si-substrateSi-substrateSi-substrate (a) Silicon base material(b) After oxidation and depositionof negativephotoresist(c) Stepper exposurePhotoresistSiO2UV-lightPatterned optical maskExposed resistSiO2Si-substrateSi-substrateSi-sub strateSiO2 SiO2(d) After development and etching of resist,chemical or plasma etch ofSiO2(e) After etching(f) Final result after removal of resistHardened resistHardened resistChemical or plasmaetchDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOS Process at a GlanceDefine active areasEtch and fill trenchesImplant well regionsDeposit and patternpolysiliconlayerImplant source and drainregions and substrate contactsCreate contact and via windowsDeposit and pattern metal layersDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOS Process Walk-Throughp+p-epi(a) Base material.

3 P+ substrate with p-epilayerp+(c) After plasma etch of insulatingtrenches using the inverse of the active area maskp+p-epiSiO23 SiN4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)Digital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOS Process Walk-ThroughSiO2(d) After trench filling, CMPplanarization, and removal of sacrificial nitride(e) After n-well and VTpadjust implantsn(f) After p-well andVTnadjust implantspDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOS Process Walk-Through(g) Afterpolysilicondepositionand etchpoly(silicon)(h) After n+source/drain andp+source/drain implants. Thesep+n+steps also dope thepolysilicon.(i) After deposition ofSiO2insulator and contact hole Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOS Process Walk-Through(j) After deposition and patterning of first Al (k) After deposition ofSiO2insulator, etching ofvia s,deposition and patterning ofsecond layer of Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessAdvanced MetalizationDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessAdvanced MetalizationDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessJan M.

4 RabaeyDesign RulesDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing Process3D PerspectivePolysiliconAluminumDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessDesign RuleslInterface between designer and Process engineerlGuidelines for constructing Process maskslUnit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)Digital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessCMOS Process LayersLayerPolysiliconMetal1 Metal2 Contact To PolyContact To DiffusionViaWell (p,n)Active Area (n+,p+)ColorRepresentationYellowGreenRed BlueMagentaBlackBlackBlackSelect (p+,n+)GreenDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessLayers in m cmos processDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessIntra-Layer Design RulesMetal2431090 WellActive33 Polysilicon22 Different PotentialSame PotentialMetal1332 Contactor ViaSelect2or62 HoleDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessTransistor Layout1253 TransistorDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessViasand Contacts121 ViaMetal toPoly ContactMetal toActive Contact1254322 Digital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessSelect Layer133222 WellSubstrateSelect35 Digital Integrated CircuitsEE141 Manufacturing

5 ProcessManufacturing ProcessCMOS Inverter LayoutAA np-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-A AA Digital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessLayout EditorDigital Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessDesign Rule Checkerpoly_not_fetto all_diff minimum spacing = Integrated CircuitsEE141 Manufacturing ProcessManufacturing ProcessSticks Diagram13 InOutVDDGNDS tick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by compaction program


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