CMOS VLSI Design - Harvey Mudd College

1 Fourth Edition cmos vlsi Design A Circuits and Systems Perspective Fourth Edition Neil H. E. Weste Macquarie University and The University of Adelaide David Money Harris Harvey Mudd College cmos vlsi Design A Circuits and Systems PerspectiveAddison-WesleyBoston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal Toronto Delhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo Editor in Chief: Michael HirschAcquisitions Editor: Matt GoldsteinEditorial Assistant: Chelsea BellManaging Editor: Jeffrey HolcombSenior Production Project Manager: Marilyn LloydMedia Producer: Katelyn BollerDirector of Marketing: Margaret WaplesMarketing Coordinator: Kathryn Ferranti Senior Manufacturing Buyer: Carol MelvilleSenior Media Buyer: Ginny MichaudText Designer.

2 Susan RaymondArt Director, Cover: Linda KnowlesCover Designer: Joyce Cosentino Wells/J Wells DesignCover Image: Cover photograph courtesy of Nick Knupffer Intel Corporation. Copyright 2009 Intel Corporation. All rights Service Vendor: Gillian Hall/The Aardvark Group Publishing ServiceCopyeditor: Kathleen Cantwell, C4 TechnologiesProofreader: Holly McLean-AldisIndexer: Jack LewisPrinter/Binder: Edwards BrothersCover Printer: Lehigh-Phoenix Color/HagerstownCredits and acknowledgments borrowed from other sources and reproduced with permission in thistextbook appear on appropriate page within text or on page interior of this book was set in Adobe Caslon and Trade 2011, 2005, 1993, 1985 Pearson Education, Inc., publishing as Addison-Wesley. Allrights reserved. Manufactured in the United States of America.

3 This publication is protected byCopyright, and permission should be obtained from the publisher prior to any prohibited reproduc-tion, storage in a retrieval system, or transmission in any form or by any means, electronic, mechani-cal, photocopying, recording, or likewise. To obtain permission(s) to use material from this work,please submit a written request to Pearson Education, Inc., Permissions Department, 501 BoylstonStreet, Suite 900, Boston, Massachusetts of the designations by manufacturers and sellers to distinguish their products are claimed astrademarks. Where those designations appear in this book, and the publisher was aware of a trade-mark claim, the designations have been printed in initial caps or all Data is on file with the Library of Congress. 10 9 8 7 6 5 4 3 2 1 EB 14 13 12 11 10 ISBN 10: 0-321-54774-8 ISBN 13: 978-0-321-54774-3 Addison-Wesleyis an imprint of To Avril, Melissa, Tamara, Nicky, Jocelyn,Makayla, Emily, Danika, Dan and Simon N.

4 W. To Jennifer, Samuel, and Abraham D. M. H. vii Preface xxv Chapter 1 Introduction A Brief History .. 1 Preview .. 6 MOS Transistors .. 6 cmos Logic .. 9 The Inverter 9 The NAND Gate 9 cmos Logic Gates 9 The NOR Gate 11 Compound Gates 11 Pass Transistors and Transmission Gates 12 Tristates 14 Multiplexers 15 Sequential Circuits 16 cmos Fabrication and Layout .. 19 Inverter Cross-Section 19 Fabrication Process 20 Layout Design Rules 24 Gate Layouts 27 Stick Diagrams 28 Design Partitioning .. 29 Design Abstractions 30 Structured Design 31 Behavioral, Structural, and Physical Domains 31 Example: A Simple MIPS Microprocessor .. 33 MIPS Architecture 33 Multicycle MIPS Microarchitectures 34 Logic Design .

5 38 Top-Level Interfaces 38 Block Diagrams 38 Hierarchy 40 Hardware Description Languages 40 Circuit Design .. 42 Contents Contents Physical Design .. 45 Floorplanning 45 Standard Cells 48 Pitch Matching 50 Slice Plans 50 Arrays 51 Area Estimation 51 Design Verification .. 53 Fabrication, Packaging, and Testing .. 54 Summary and a Look Ahead 55 Exercises 57 Chapter 2 MOS Transistor Theory Introduction .. 61 Long-Channel I-V Characteristics .. 64 C-V Characteristics .. 68 Simple MOS Capacitance Models 68 Detailed MOS Gate Capacitance Model 70 Detailed MOS Diffusion Capacitance Model 72 Nonideal I-V Effects .. 74 Mobility Degradation and Velocity Saturation 75 Channel Length Modulation 78 Threshold Voltage Effects 79 Leakage 80 Temperature Dependence 85 Geometry Dependence 86 Summary 86 DC Transfer Characteristics.

6 87 Static cmos Inverter DC Characteristics 88 Beta Ratio Effects 90 Noise Margin 91 Pass Transistor DC Characteristics 92 Pitfalls and Fallacies .. 93 Summary 94 Exercises 95 Chapter 3 cmos Processing Technology Introduction .. 99 cmos Technologies .. 100 Wafer Formation Photolithography Well and Channel Formation Silicon Dioxide (SiO2) Isolation Gate Oxide Gate and Source/Drain Formations Contacts and Metallization Passivation Metrology Design Rules .. Design Rule Background Scribe Line and Other Structures MOSIS Scalable cmos Design Rules Micron Design Rules Process Enhancements .. Transistors Interconnect Circuit Elements Beyond Conventional cmos CAD Issues.

7 Design Rule Checking (DRC) Extraction Issues .. Antenna Rules Layer Density Rules Resolution Enhancement Rules Metal Slotting Rules Yield Enhancement Guidelines and Fallacies .. Perspective .. 137 Summary 139 Exercises 139 Chapter 4 .. Definitions Timing Optimization Response .. Delay Model .. Effective Resistance Gate and Diffusion Capacitance Equivalent RC Circuits Transient Response Elmore Delay Layout Dependence of Capacitance Determining Effective Resistance Delay Model .. Logical Effort Parasitic Delay Delay in a Logic Gate Drive Extracting Logical Effort from Datasheets Limitations to the Linear Delay Model Effort of Paths .. Delay in Multistage Logic Networks Choosing the Best Number of Stages Example Summary and Observations Limitations of Logical Effort Iterative Solutions for Sizing Analysis Delay Models.

8 Slope-Based Linear Model Nonlinear Delay Model Current Source Model and Fallacies .. Perspective .. 175 Summary 176 Exercises 176 Chapter 5 .. Definitions Examples Sources of Power Dissipation Power .. Activity Factor Capacitance Voltage Frequency Short-Circuit Current Resonant Circuits Power .. Static Power Sources Power Gating Multiple Threshold Voltages and Oxide Thicknesses Variable Threshold Voltages Input Vector Control Optimization .. Minimum Energy Minimum Energy-Delay Product Minimum Energy Under a Delay Constraint Power Architectures .. Microarchitecture Parallelism and Pipelining Power Management Modes and Fallacies .. Perspective .. 207 Summary 209 Exercises 209 Chapter 6.

9 Wire Geometry Example: Intel Metal Stacks Modeling .. Resistance Capacitance Inductance Skin Effect Temperature Dependence Impact .. Delay Energy Inductive Effects An Aside on Effective Resistance and Elmore Delay Engineering .. Width, Spacing, and Layer Repeaters Crosstalk Control Low-Swing Signaling Regenerators Effort with Wires .. and Fallacies .. 237 Summary 238 Exercises 238 ContentsxiiChapter 7 .. Supply Voltage Temperature Process Variation Design Corners .. Reliability Terminology Oxide Wearout Interconnect Wearout Soft Errors Overvoltage Failure Latchup .. Transistor Scaling Interconnect Scaling International Technology Roadmap for Semiconductors Impacts on Design Analysis of Variability.

10 Properties of Random Variables Variation Sources Variation Impacts Design .. Adaptive Control Fault Tolerance and Fallacies .. Perspective .. 278 Summary 284 Exercises 284 Chapter 8 Circuit .. SPICE Tutorial .. Sources and Passive Components Transistor DC Analysis Inverter Transient Analysis Subcircuits and Measurement Optimization Other HSPICE Commands Models .. Level 1 Models Level 2 and 3 Models BSIM Models Diffusion Capacitance Models Design Corners Characterization .. I-V Characteristics Threshold Voltage Gate Capacitance Parasitic Capacitance Effective Resistance Comparison of Processes Process and Environmental Sensitivity Characterization .. Path Simulations DC Transfer Characteristics Logical Effort Power and Energy Simulating Mismatches Monte Carlo Simulation Simulation.