Lecture 1: Circuits & Layout - cmosvlsi.com

1 Introduction toCMOS VLSID esignLecture 1: Circuits & LayoutDavid HarrisHarvey Mudd CollegeSpring 20041: Circuits & LayoutSlide 2 cmos vlsi DesignOutlineqA Brief HistoryqCMOS Gate DesignqPass TransistorsqCMOS Latches & Flip-FlopsqStandard Cell LayoutsqStick Diagrams1: Circuits & LayoutSlide 3 cmos vlsi DesignA Brief Historyq1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instrumentsq2003 Intel Pentium 4 processor(55 million transistors) 512 Mbit DRAM (> billion transistors)q53% compound annual growth rate over 45 years No other technology has grown so fast so longqDriven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society1: Circuits & LayoutSlide 4 cmos vlsi DesignAnnual Salesq1018transistors manufactured in 2003 100 million for every human on the planet0501001502001982198419861988199019 9219941996199820002002 YearGlobal Semiconductor Billings(Billions of US$)1: Circuits & LayoutSlide 5 cmos vlsi DesignInvention of the TransistorqVacuum tubes ruled in first half of 20thcentury Large, expensive, power-hungry, unreliableq1947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs Read Crystal FireBy Riordan, Hoddeson1.

2 Circuits & LayoutSlide 6 cmos vlsi DesignTransistor TypesqBipolar transistors npn or pnpsilicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration densityqMetal Oxide Semiconductor Field Effect Transistors nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration1: Circuits & LayoutSlide 7 cmos vlsi DesignMOS Integrated Circuitsq1970 s processes usually had only nMOS transistors Inexpensive, but consume power while idleq1980s-present: cmos processes for low idle powerIntel 1101 256-bit SRAMI ntel 4004 4-bit Proc1: Circuits & LayoutSlide 8 cmos vlsi DesignMoore s Lawq1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 monthsYearTransistors4004800880808086802 86 Intel386 Intel486 PentiumPentium ProPentium IIPentium IIIP entium 41,00010,000100,0001,000,00010,000,00010 0,000,0001,000,000,000197019751980198519 9019952000 Integration LevelsSSI: 10 gatesMSI: 1000 gatesLSI: 10,000 gatesVLSI: > 10k gates1: Circuits & LayoutSlide 9 cmos vlsi DesignCorollariesqMany other factors grow exponentially Ex.

3 Clock frequency, processor performanceYear1101001,00010,00019701975 1980198519901995200020054004800880808086 80286 Intel386 Intel486 PentiumPentium Pro/II/IIIP entium 4 Clock Speed (MHz)1: Circuits & LayoutSlide 10 cmos vlsi DesignCMOS Gate DesignqActivity: Sketch a 4-input cmos NAND gate1: Circuits & LayoutSlide 11 cmos vlsi DesignCMOS Gate DesignqActivity: Sketch a 4-input cmos NOR gateABCDY1: Circuits & LayoutSlide 12 cmos vlsi DesignComplementary CMOSqComplementary cmos logic gates nMOS pull-down network pMOS pull-up network static CMOSpMOSpull-upnetworkoutputinputsnMOSpu ll-downnetworkX (crowbar)0 Pull-down ON1Z (float)Pull-down OFFPull-up ONPull-up OFF1: Circuits & LayoutSlide 13 cmos vlsi DesignSeries and ParallelqnMOS: 1 = ONqpMOS: 0 = ONqSeries: both must be ONqParallel: either can be ON(a)ababg1g200ab01ab10ab11 OFFOFFOFFON(b)ababg1g200ab01ab10ab11 ONOFFOFFOFF(c)ababg1g200 OFFONONON(d)ONONONOFFab0ab1ab1101ab00ab0 ab1ab1101abg1g21: Circuits & LayoutSlide 14 cmos vlsi DesignConduction ComplementqComplementary cmos gates always produce 0 or 1qEx: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOSqRule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallelABY1.

4 Circuits & LayoutSlide 15 cmos vlsi DesignCompound GatesqCompound gatescan do any inverting functionqEx: (AND-AND-OR-INVERT, AOI22)YABCD=+ggABCDABCDABCDABCDBDYACACAB CDBDY(a)(c)(e)(b)(d)(f)1: Circuits & LayoutSlide 16 cmos vlsi DesignExample: O3 AIq()YABCD=++g1: Circuits & LayoutSlide 17 cmos vlsi DesignExample: O3AI q()YABCD=++gABYCDDCBA1: Circuits & LayoutSlide 18 cmos vlsi DesignSignal StrengthqStrengthof signal How close it approximates ideal voltage sourceqVDDand GND rails are strongest 1 and 0qnMOS pass strong 0 But degraded or weak 1qpMOS pass strong 1 But degraded or weak 0qThus nMOS are best for pull-down network1: Circuits & LayoutSlide 19 cmos vlsi DesignPass TransistorsqTransistors can be used as switchesgsdgsd1: Circuits & LayoutSlide 20 cmos vlsi DesignPass TransistorsqTransistors can be used as switchesgsdg = 0sdg = 1sd0strong 0 InputOutput1degraded 1gsdg = 0sdg = 1sd0degraded 0 InputOutputstrong 1g = 1g = 1g = 0g = 01: Circuits & LayoutSlide 21 cmos vlsi DesignTransmission GatesqPass transistors produce degraded outputsqTransmission gatespass both 0 and 1 well1: Circuits & LayoutSlide 22 cmos vlsi DesignTransmission GatesqPass transistors produce degraded outputsqTransmission gatespass both 0 and 1 wellg = 0, gb = 1abg = 1, gb = 0ab0strong 0 InputOutput1strong 1ggbababggbabggbabggbg = 1, gb = 0g = 1, gb = 01.

5 Circuits & LayoutSlide 23 cmos vlsi DesignTristatesqTristate bufferproduces Z when not enabled11011000 YAENAYENAYENEN1: Circuits & LayoutSlide 24 cmos vlsi DesignTristatesqTristate bufferproduces Z when not enabled111001Z10Z00 YAENAYENAYENEN1: Circuits & LayoutSlide 25 cmos vlsi DesignNonrestoring TristateqTransmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to YAYENEN1: Circuits & LayoutSlide 26 cmos vlsi DesignTristate InverterqTristate inverter produces restored output Violates conduction complement rule Because we want a Z outputAYENEN1: Circuits & LayoutSlide 27 cmos vlsi DesignTristate InverterqTristate inverter produces restored output Violates conduction complement rule Because we want a Z outputAYENAYEN = 0Y = 'Z'YEN = 1Y = AAEN1: Circuits & LayoutSlide 28 cmos vlsi DesignMultiplexersq2:1 multiplexerchooses between two inputsX11X011X00X0YD0D1S01SD0D1Y1: Circuits & LayoutSlide 29 cmos vlsi DesignMultiplexersq2:1 multiplexer chooses between two inputs1X110X0111X000X0YD0D1S01SD0D1Y1: Circuits & LayoutSlide 30 cmos vlsi DesignGate-Level Mux DesignqqHow many transistors are needed?

6 10 (too many transistors)YSDSD=+1: Circuits & LayoutSlide 31 cmos vlsi DesignGate-Level Mux DesignqqHow many transistors are needed? 2010 (too many transistors)YSDSD=+44D1D0SY4222Y2D1D0S1: Circuits & LayoutSlide 32 cmos vlsi DesignTransmission Gate MuxqNonrestoring mux uses two transmission gates1: Circuits & LayoutSlide 33 cmos vlsi DesignTransmission Gate MuxqNonrestoring mux uses two transmission gates Only 4 transistorsSSD0D1YS1: Circuits & LayoutSlide 34 cmos vlsi DesignInverting MuxqInverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thingqNoninverting multiplexer adds an inverterSD0D1 YSD0D1Y01 SYD0D1 SSSSSS1: Circuits & LayoutSlide 35 cmos vlsi Design4:1 Multiplexerq4:1 mux chooses one of 4 inputs using two selects1: Circuits & LayoutSlide 36 cmos vlsi Design4:1 Multiplexerq4.

7 1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristatesS0D0D1010101YS1D2D3D0D1D2D3YS1S 0S1S0S1S0S1S01: Circuits & LayoutSlide 37 cmos vlsi DesignD LatchqWhen CLK = 1, latch is transparent D flows through to Q like a bufferqWhen CLK = 0, the latch is opaque Q holds its old value independent of transparent latchor level-sensitive latchCLKDQL atchDCLKQ1: Circuits & LayoutSlide 38 cmos vlsi DesignD Latch DesignqMultiplexer chooses D or old Q10 DCLKQCLKCLKCLKCLKDQQQ1: Circuits & LayoutSlide 39 cmos vlsi DesignD Latch OperationCLK = 1 DQQCLK = 0 DQQDCLKQ1: Circuits & LayoutSlide 40 cmos vlsi DesignD Flip-flopqWhen CLK rises, D is copied to QqAt all other times, Q holds its positive edge-triggered flip-flop, master-slave flip-flopFlopCLKDQDCLKQ1: Circuits & LayoutSlide 41 cmos vlsi DesignD Flip-flop DesignqBuilt from master and slave D latchesQMCLKCLKCLKCLKQCLKCLKCLKCLKDL atchLatchDQQMCLKCLK1: Circuits & LayoutSlide 42 cmos vlsi DesignD Flip-flop OperationCLK = 1 DCLK = 0 QDQMQMQDCLKQ1: Circuits & LayoutSlide 43 cmos vlsi DesignRace ConditionqBack-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failureor race conditionCLK1DQ1 FlopFlopCLK2Q2 CLK1 CLK2Q1Q21.

8 Circuits & LayoutSlide 44 cmos vlsi DesignNonoverlapping ClocksqNonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skewqWe will use them in this class for safe design Industry manages skew more carefully instead 1 1 1 1 2 2 2 2 2 1 QMQD1: Circuits & LayoutSlide 45 cmos vlsi DesignGate LayoutqLayout can be very time consuming Design gates to fit together nicely Build a library of standard cellsqStandard cell design methodology VDDand GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts1: Circuits & LayoutSlide 46 cmos vlsi DesignExample: Inverter1: Circuits & LayoutSlide 47 cmos vlsi DesignExample: NAND3qHorizontal N-diffusion and p-diffusion stripsqVertical polysilicon gatesqMetal1 VDDrail at topqMetal1 GND rail at bottomq32 by 40 1: Circuits & LayoutSlide 48 cmos vlsi DesignStick DiagramsqStick diagramshelp plan Layout quickly Need not be to scale Draw with color pencils or dry-erase markers1: Circuits & LayoutSlide 49 cmos vlsi DesignWiring TracksqA wiring trackis the space required for a wire 4 width, 4 spacing from neighbor = 8 pitchqTransistors also consume one wiring track1: Circuits & LayoutSlide 50 cmos vlsi DesignWell spacingqWells must surround transistors by 6 Implies 12 between opposite transistor flavors Leaves room for one wire track1.

9 Circuits & LayoutSlide 51 cmos vlsi DesignArea EstimationqEstimate area by counting wiring tracks Multiply by 8 to express in 1: Circuits & LayoutSlide 52 cmos vlsi DesignExample: O3 AIqSketch a stick diagram for O3AI and estimate area ()YABCD=++g1: Circuits & LayoutSlide 53 cmos vlsi DesignExample: O3 AIqSketch a stick diagram for O3AI and estimate area ()YABCD=++g1: Circuits & LayoutSlide 54 cmos vlsi DesignExample: O3 AIqSketch a stick diagram for O3AI and estimate area ()YABCD=++g