Combinational Logic Gates in CMOS

1 Combinational Logic Gates in CMOSR eferences:Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey, Prentice Hall UCBP rinciples of CMOS VLSI Design: A Systems Perspective, N. H. E. Weste, K. Eshraghian, Addison WesleyAdapted from: EE216A Lecture Notes by Prof. K. Bult UCLAC ombinational vs. Sequential LogicCombinationalSequentialStateOut = f(In)Out = f(In, State)State is related to previous inputsStored in registers, memory etcOverview Static CMOS Complementary CMOS Ratioed Logic Pass Transistor/Transmission gate Logic Dynamic CMOS Logic Domino np-CMOSS tatic CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDDor VSSvia a low-resistive path The outputs of the Gates assume at all times the value of the Boolean function, implemented by the circuit In contrast, a dynamic circuit relies on temporary storage of signal values on the capacitance of high impedance circuit nodesDigital Gates Fundamental Parameters Area and Complexity Performance Power Consumption Robustness and ReliabilityWhat Can Go Wrong in CMOS Logic ?

2 Incorrect or insufficient power supplies Power supply noise Noise on gate input Faulty connections between transistors Clock frequency too high or circuit too slowComplementary CMOS is prettysafe against theseHow about Ratioed or Dynamic Logic ? All the previous and Incorrect ratios in ratioed Logic Charge sharing in dynamic Logic Incorrect clocking in dynamic logicComplementary CMOSPUNPDNin1in2in3in1in2in3 VDDVSSF = GNMOS onlyPMOS onlyPUN and PDN are dual networksNMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is highXYABX = Y if A = 1 and B = 1, , AB = 1 NMOS passes a strong 0 but a weak 1 XYABX = Y if A = 1 or B = 1, , A + B = 1 NMOS Transistors in Series/Parallel Connection Connect Y to GNDXYABX = 0 if A = 1 and B = 1, , = 1 Implement the complement of PDNXYABX = 0 if A = 1 or B = 1.

3 A + B = 1X = = A + BPMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is lowXYABX = Y if A = 0 and B = 0or A + B = 1or = 1 PMOS passes a strong 1 but a weak 0 XYABX = Y if A = 0 or B = = 1A + B = 1 PMOS Transistors in Series/Parallel Connection Connect Y to VDDXYABX = 1 if A = 0 and B = 0 Combine series PDN and parallel PUN or parallel PDN and series PUN to complete the Logic design to output good 1 and 0 XYABX = 1 if A = 0 or B = 0X = A + B = X = = A + BComplementary CMOS Logic Style Construction PUN is the DUAL of PDN (can be shown using DeMorgan s Theorems)BABA=+BAAB+= The complementary gate is inverting Implements nand , NOR, .. Non-inverting boolean function needs an inverter,..),,(.

4 ,,(321321inininFinininG The nand CircuitBABA+11100101 ABBOutABA.,..),,(,..),,(321321inininFini ninG BAG.:GND toconnected PDN=ABBAFVDD=+=: toconnected PUNBA10000101 ABABThe NOR CircuitA + BA . BBA+= Output Example gate : COMPLEX CMOS GATEVDDABCDDABCOUT = D + A (B+C)F = (( ) + C.(A+B)) = carryBCAA outputABBBCAABB outputABCABACS ymmetrical !RemoveredundancyF = (ABC+ABC+ABC+ABC) = sumA-B-AB-C-A-BABCC-CBA-B-A-BAB-AoutputF ull Adder CircuitABBCABCBAAABCAABCBCCBA-sum-carry4 -input nand GateIn1 In2 In3 In4 VDDGNDO utln2ln1ln2 Outln1ln4ln3ln4ln3 Standard Cell Layout MethodologyVDDVSSW ellsignalsRouting Channelmetal1polysiliconTwo Versions of (a+b).cacba b cxxGNDVDDVDDGND(a) Input order {a c b}(b) Input order {a b c} Logic GraphVDDcaxbcabGNDxVDDxcbaijijPDNPUNC onsistent Euler Path{a b c}Example.)

5 X = ab+cdGNDxabcdVDDxGNDxabcdVDDx(a) Logic graphs for (ab+cd)(b) Eule r Paths {a b c d}acdxVDDGND(c) stick diagram for ordering {a b c d}bProperties of Complementary CMOS Gates High noise margin VOHand VOLare at VDDand GND, respectively No static power consumption In steady state, no direct path between VDDand VSS Comparable rise and fall times under appropriate scaling of PMOS and NMOS transistorsTransistor Sizing For symmetrical response (dc, ac) For performance Input dependent Focus on worst-casePropagation Delay Analysis - The Switch ModelAnalysis of Propagation Delay Assume CLdominates Assume Rn= Rp= resistance of minimum sized NMOS inverter For tpLH Worst case when only one PMOS pulls up the output node tpLH RpCL For tpHL Worst case when two NMOS in series tpHL 2 RnCL3-Input nand Gateincoutinbinarise-time: 1 transistor (simple)fall-time: 3 transistor in seriesfor linear approximation: take 3xRon3-Input nand GateincoutinbinaIf n= 3 pfor equal fall and rise time:Take Wn= WpIf n= 2 pfor equal fall and rise time.

6 Take Wn= (3/2)WpDesign for Worst Case3-input nand gate with Parasitic CapacitorsincoutinbinaCp+loadCaCbCcP1P2P 3N3N2N1 Worst Case ApproximationUsing Lumped RC Model))(()(321loadpcbaNNNpulldownpulldow ndfCCCCRRRCRt++++ ++= =(We ignore the constant term or )Penfield-Rubenstein Model(Elmore Delay Model)td= RiCiwith: Ci= capacitance at node iRi= total resistance between Ciand supplytdf= [RN1Ca] + [(RN1+ RN2)Cb] + [(RN1+ RN2+ RN3)(Cc+ Cp+load)]Distributed RC )1(nCnRnnRCtn + =Worst case under lumped model: tn= [RNICa] + [(RN1+RN2)Cb] + [(RN1+RN2+RN3)Cc] +[(RN1+ RN2 + RN3)Cp+load]RNC n(n+1)/2 + [(RN1+RN2+RN3)Cp+load]With RN1= RN2 = RN3= RNand Ca= Cb= Cc = Cn transistors in seriesRP-ModelLumped-ModelRNC n2+ [(RN1+RN2+RN3)Cp+load]Macro Modelingtd = [RN1Ca] + [(RN1+RN2)Cb] + [(RN1+ RN2+ RN3)Cc] +[(RN1+ RN2+ RN3)Cp+ [(RN1+ RN2+ RN3)Cload]Internal delayExternal loadtd= Td, internal+ x CloadEffect of LoadingCL= td, internal+ x CloadEffect of Fan-In and Fan-Outon Delayln2ln1ln2 Outln1ln4ln3ln4ln3 Fan-out: number of Gates connected 2 gate capacitance per fan-out Fan-in.]

7 Number of inputs to a gate Quadratic effect due to increasing resistance and capacitance FOaFIaFIatd3221++=tpas a function of (nsec)tpHLtptpLHlinearquadraticAVOID LARGE FAN-IN Gates ! (Typically not more than FI < 4)Example3-Input nand gate with Parasitic CapacitorsincoutinbinaCp+loadCaCbCcP1P2P 3Rn= Worst Case Approximation by Lumped Modeltdr = Rpx (Cc+Cp+load) = 10000 x 10-12= Rpulldownx Cpulldown= (RN1+ RN2+ RN3) x (Ca+ Cb + (Cc+ Cp+load))= (3 x 5000) x (3 x + + ) x 10-12= Modeltdr=Rpx (Cc+Cp+load) = 10000 x 10-12= tdf= [RN1Ca] + [(RN1+ RN2)Cb] + [(RN1 + RN2+ RN3)(Cc+ Cp+load)]= 5000 x + 10000 x + 15000 x = Case Approximation by Lumped Modeltdr = Rpx (Cc+Cp+load) = 10000 x 10-12= Rpulldownx Cpulldown= (RN1+ RN2+ RN3) x (Ca+ Cb + (Cc+ Cp+load))= (3 x 2500) x (3 x + + ) x 10-12= Wn= 2 WpPenfield-Rubenstein Modeltdr=Rpx (Cc+Cp+load) = 10000 x 10-12= tdf= [RN1Ca] + [(RN1+ RN2)Cb] + [(RN1 + RN2+ RN3)]

8 (Cc+ Cp+load)]= 2500 x + 5000 x + 7500 x = Wn= 2 WpRewriting Penfield-Rubenstein Equationtd= RiiCdownstream-iwith: Cdownstream-i= downstream capacitance at node iRii= resistance at node itd= [RN1Ca] + [(RN1+ RN2)Cb] + [(RN1+ RN2+ RN3)(Cc+ Cp+load)]td= [RN1(Ca +Cb+Cc +Cp+load)] + [RN2 (Cb+Cc +Cp+load)] + [RN3(Cc+ Cp+load)]Progressive Sizing When parasitic capacitance is significant ( , when fan-in is large), needs to consider distributed RC effect Increasing the size of M1 has the largest impact in terms of delay reduction M1> M2> M3> .. > MNln3lnNOutln1ln2M1M2M3 MNDelay Optimization by Transistor Orderingln3lnNOutln1ln2M1M2M3 MNCritical signal next to supplyCritical pathln3lnNOutln1ln2M1M2M3 MNCritical signal next to outputCritical path