CS250 VLSI Systems Design Lecture 8: Memory

1 Lecture 8, MemoryCS250, UC Berkeley, Fall 2010CS250 VLSI Systems DesignLecture 8: MemoryJohn Wawrzynek, Krste Asanovic,withJohn LazzaroandYunsup Lee (TA)UC BerkeleyFall 2010CS250, UC Berkeley, Fall 2010 Lecture 8, MemoryCMOS BistableCross-coupled inverters used to hold state in CMOS Static storage in powered cell, no refresh neededIf a storage node leaks or is pushed slightly away from correct value, non-linear transfer function of high-gain inverter removes noise and recirculates correct valueTo write new state, have to force nodes to opposite state2DD 1 0 DD 0 1 Flip StateCS250, UC Berkeley, Fall 2010 Lecture 8, MemoryCMOS Transparent LatchLatch transparent (output follows input) when clock is high, holds last value when clock is low3 Optional Input BufferOptional Output BufferDQClkClkClkClkDQClkDQClkSchematic SymbolsTransparent on clock lowTransmission gate switch with both pMOS and nMOS passes both ones and zeros wellCS250, UC Berkeley, Fall 2010 Lecture 8, MemoryLatch Operation4DQ1100 DClock HighLatch TransparentDQ0011 QClock LowLatch HoldingCS250, UC Berkeley, Fall 2010 Lecture 8, MemoryFlip-Flop as Two Latches5 QClkClkClkClkHoldDQClkClkClkClkSampleQDC lkClkSchematic SymbolsThis is how standard cell flip-flops are built(usually with extra in/out buffers) CS250 , UC Berkeley, Fall 2010 Lecture 8, MemorySmall Memories from Stdcell LatchesAdd additional ports by replicating read and write port logic (multiple write ports need mux in front of latch)

2 Expensive to add many ports6 Write Address DecoderRead Address DecoderClkWrite AddressWrite DataRead AddressClkCombinational logic for read port (synthesized)Optional read output latchData held in transparent-low latchesWrite by clocking latchCS250, UC Berkeley, Fall 2010 Lecture 8, Memory6-Transistor SRAM (Static RAM)7 Large on-chip memories built from arrays of static RAM bitcells, where each bit cell holds a bistable (cross-coupled inverters) and two access clocking and access logic factored out into peripheryBitBitWordlineCS250, UC Berkeley, Fall 2010 Lecture 8, MemoryIntel s 22nm SRAM cell8!"#$%&''(&&%)*%!+,-%."/$%012#!"!#$% &'$()%*+,%)' ,)*%/012%3,..%(4%5678(49%3(73&(*)%7,:67* ,;%*6%;-*, um2 SRAM cell for high density um2 SRAM cell for low voltage applications[Bohr, Intel, Sept 2009] CS250 , UC Berkeley, Fall 2010 Lecture 8, MemoryGeneral SRAM Structure9 Address Decode and Wordline DriverDifferential Read Sense AmplifiersDifferential Write DriversBitline PrechargersAddressWrite DataRead DataUsually maximum of 128-256 bits per row or columnClkClkWrite EnableCS250, UC Berkeley, Fall 2010 Lecture 8, MemoryAddress Decoder Structure10A1A0A3A22.)

3 4 PredecodersClocked Word Line EnableAddressWord Line 0 Word Line 1 Word Line 15 Unary 1-of-4 encodingCS250, UC Berkeley, Fall 2010 Lecture 8, MemoryRead Cycle111) Precharge bitlines and senseamp1)2) Pulse wordlines, develop bitline differential voltage2)Bitline differentialClkBit/BitWordlineSenseData/ Data3) Disconnect bitlines from senseamp, activate sense pulldown, develop full-rail data signals3)Full-rail swingPulses generated by internal self-timed signals, often using replica circuits representing critical pathsClkSenseDataDataFrom DecoderWordline ClockPrechargersSense AmpStorage CellsBitBitOutput Set-Reset LatchCS250, UC Berkeley, Fall 2010 Lecture 8, MemoryWrite Cycle121) Precharge bitlines1)ClkBit/BitWordline2) Open wordline, pull down one bitline full rail2)ClkWrite DataFrom DecoderWordline ClockPrechargersStorage CellsBitBitWrite EnableWrite-enable can be controlled on a per-bit level.

4 If bit lines not driven during write, cell retains value (looks like a read to the cell). CS250 , UC Berkeley, Fall 2010 Lecture 8, MemoryColumn-Muxing at Sense Amps13 Sel1 ClkSel0 From DecoderWordline ClockSense AmpDifficult to pitch match sense amp to tight SRAM bit cell spacing so often 2-8 columns share one sense amp. Impacts power dissipation as multiple bitline pairs swing for each bit , UC Berkeley, Fall 2010 Lecture 8, MemoryBuilding Larger Memories14 Bit cellsDecI/OBit cellsI/OBit cellsDecBit cellsBit cellsDecI/OBit cellsI/OBit cellsDecBit cellsBit cellsDecI/OBit cellsI/OBit cellsDecBit cellsBit cellsDecI/OBit cellsI/OBit cellsDecBit cellsLarge arrays constructed by tiling multiple leaf arrays, sharing decoders and I/O , sense amp attached to arrays above and belowLeaf array limited in size to 128-256 bits in row/column due to RC delay of wordlines and bitlinesAlso to reduce power by only activating selected sub-bankIn larger memories, delay and energy dominated by I/O wiringCS250, UC Berkeley, Fall 2010 Lecture 8, MemoryAdding More Ports15 BitABitAWordlineAWordlineBBitBBitBWordli neRead BitlineDifferential Read or Write portsOptional Single-ended Read portCS250.

5 UC Berkeley, Fall 2010 Lecture 8, MemoryMemory CompilersIn ASIC flow, Memory compilers used to generate layout for SRAM blocks in designOften hundreds of Memory instances in a modern SoCMemory generators can also produce built-in self-test (BIST) logic, to speed manufacturing testing, and redundant rows/columns to improve yieldCompiler can be parameterized by number of words, number of bits per word, desired aspect ratio, number of sub banks, degree of column muxing, , delay, and energy consumption complex function of Design parameters and generation algorithmWorth experimenting with Design spaceUsually only single read or write port SRAM and one read and one write SRAM generators in ASIC library16CS250, UC Berkeley, Fall 2010 Lecture 8, MemorySmall Memories17 Compiled SRAM arrays usually have a high overhead due to peripheral circuits, BIST, redundancy. Small memories are usually built from latches and/or flip-flops in a stdcell flowCross-over point is usually around 1K bits of storageShould try Design both waysCS250, UC Berkeley, Fall 2010 Lecture 8, MemoryMemory Design Patterns18CS250, UC Berkeley, Fall 2010 Lecture 8, MemoryMultiport Memory Design PatternsOften we require multiple access ports to a common memoryTrue Multiport MemoryAs describe earlier in Lecture , completely independent read and write port circuitryBanked Multiport MemoryInterleave lesser-ported banks to provide higher bandwidthStream-Buffered Multiport MemoryUse single wider access port to provide multiple narrower streaming portsCached Multiport MemoryUse large single-port main Memory , but add cache to service 19CS250, UC Berkeley, Fall 2010 Lecture 8, MemoryTrue Multiport MemoryProblem.

6 Require simultaneous read and write access by multiple independent agents to a shared common : Provide separate read and write ports to each bit cell for each requesterApplicability: Where unpredictable access latency to the shared Memory cannot be : High area, energy, and delay cost for large number of ports. Must define behavior when multiple writes on same cycle to same word ( , prohibit, provide priority, or combine writes).20CS250, UC Berkeley, Fall 2010 Lecture 8, MemoryTrue Multiport Example: Itanium-2 RegfileIntel Itanium-2 [Fetzer et al, IEEE JSSCC 2002]211434 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002 Fig. 2. Register file circuit and timing 3. Double-pumped pulse clock generator circuit and timing of logic. To prevent pulse degradation, a pulsewidth-con-trol feedback delay is inserted between the decoder and the wordline.

7 The word line muxing, internal to the register, capturespulses during the write phase of the system clock and holds thewrite signal at high value until the end of the phase, giving thewrite mechanism more than a pulse width to write data into theregister. Since writes are single ended through a nFET pass gate,one leg of the cell is floated using a virtual ground, which im-proves timing and cell writeability. This technique is demon-strated in silicon to work integer datapath bypassing is divided into four stages, toafford more timing critical inputs the least possible logic delayto the consuming ALUs. Critical L1 cache return data must flowthrough only one level of muxing before arriving at the ALU in-puts, while DET and WRB data, available from staging latches,have the longest logic path to the ALUs. This allows the by-passing of operands from 34 possible results to occur in a halfclock cycle, enabling a single-cycle cache access and instruc-tion , UC Berkeley, Fall 2010 Lecture 8, MemoryItanium-2 Regfile Timing22 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.

8 37, NO. 11, NOVEMBER 20021433A Fully Bypassed Six-Issue Integer Datapath andRegister File on the Itanium-2 MicroprocessorEric S. Fetzer, Mark Gibson, Anthony Klein, Naomi Calick, Chengyu Zhu, Eric Busta, and Baker MohammadAbstract The six-issue integer datapath of the second-genera-tion Itanium Microprocessor is described. Pulse techniques enablea high-speed, 20-ported, 128-entry, 65-bit register file with only12 wordlines per register. A four-stage operand bypass networkachieves a fully bypassed Design with operands sourced from 34 lo-cations with 16 destinations. To control this network, over 280 by-pass comparators are utilized. Using half a clock for execution andhalf a clock for bypass, each result is available for the next instruc-tion. Functional units are pre-enabled, reducing power consump-tion by 15% while eliminating a stage of result muxing and im-proving performance.

9 The part is fabricated in a six-layer, 18-mprocess and operates at GHz at V, consuming less than 130W in about 420 Terms Digital integrated circuits, integrated circuit de-sign, integrated circuit noise, microprocessors, INTRODUCTIONTHE Itanium-2 microprocessor, the second implementa-tion of the Itanium architecture, features an explicitlyparallel architecture. This architecture lends itself to a highlysuperscalar implementation. Highly superscalar designs requirelarger register files (RFs) to feed multiple execution unitsand complex bypass networks to keep data freely movingthrough the system. The Itanium-2 microprocessor incorporatesa six-issue integer datapath (IEU) with a 20-ported, 128-entry,65-bit-wide RFs. To prevent data hazards, integer operandsare fully bypassed through four stages of bypass multiplexingwith each of the 12 integer operands and four data cacheaddresses sourced from 34 possible results (RF, instructionfield, two L1 data caches, six arithmetic and logic (ALU) EXEstages (Fig.))

10 1), eight DET stages, eight WRB-stage integers,six WRB-stage multimedia, and various architected registers).All IEU operations require a half cycle for execution and ahalf cycle for bypass, allowing each ALU result to be used inthe next cycle as a source for ALU or data cache this paper, we detail circuit and analysis techniques used tocomplete this high-performance received March 15, 2002; revised June 10, S. Fetzer, M. Gibson, A. Klein, and E. Busta are with Hewlett-PackardCompany, Fort Collins, CO 80528-9599 USA (e-mail: Calick and C. Zhu are with Intel Corporation, Fort Collins, CO 80525 USA(e-mail: Mohammad is with Intel Corporation, Chandler, AZ 85226 USA Object Identifier 1. IEU state and timing 20-ported RF is mmand incorporates 12 read andeight write ports. To accomplish all required bypassing, RFreads occur simultaneously with the first two stages of bypassand ALU execution (Fig.)