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Cyclone V Device Handbook - intel.com

Cyclone V Device HandbookVolume 1: Device Interfaces and IntegrationSubscribeSend Innovation DriveSan Jose, CA Array Blocks and Adaptive Logic Modules in Cyclone V 1-1 LAB .. 1-1 MLAB .. 1-2 Local and Direct Link Interconnects .. 1-3 LAB Control 1-4 ALM Resources .. 1-5 ALM Output .. 1-6 ALM Operating Modes .. 1-8 Normal Mode ..1-8 Extended LUT Mode .. 1-8 Arithmetic Mode .. 1-8 Shared Arithmetic Mode ..1-10 Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices Revision 1-11 Embedded Memory Blocks in Cyclone V 2-1 Types of Embedded 2-1 Embedded Memory Capacity in Cyclone V 2-1 Embedded Memory Design Guidelines for Cyclone V 2-2 Guideline: Consider the Memory Block 2-2 Guideline: Implement External Conflict 2-3 Guideline: Customize Read-During-Write 2-3 Guideline: Consider Power-Up State and Memory 2-7 Guideline: Control Clocking to Reduce Power Memory 2-7 Embedded Memory Port 2-9 Embedded Memory 2-10 Embedded Memory Clocking 2-12 Clocking Modes for Each Memory 2-12 Asynchronous Clears in Clocking 2-13 Output Read Data in Simultaneous Clock Enables in Clocking Bit in Memory Enable in Embedded Memory 2-14 Byte Enable Controls in Memory 2-14 Data Byte 2-15 RAM Blocks 2-15 Memory Blocks Packed Mode Blocks Address Clock

RS OCT without Calibration in Cyclone V Devices.....5-39 RS OCT with Calibration in Cyclone V Devices.....5-41

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Transcription of Cyclone V Device Handbook - intel.com

1 Cyclone V Device HandbookVolume 1: Device Interfaces and IntegrationSubscribeSend Innovation DriveSan Jose, CA Array Blocks and Adaptive Logic Modules in Cyclone V 1-1 LAB .. 1-1 MLAB .. 1-2 Local and Direct Link Interconnects .. 1-3 LAB Control 1-4 ALM Resources .. 1-5 ALM Output .. 1-6 ALM Operating Modes .. 1-8 Normal Mode ..1-8 Extended LUT Mode .. 1-8 Arithmetic Mode .. 1-8 Shared Arithmetic Mode ..1-10 Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices Revision 1-11 Embedded Memory Blocks in Cyclone V 2-1 Types of Embedded 2-1 Embedded Memory Capacity in Cyclone V 2-1 Embedded Memory Design Guidelines for Cyclone V 2-2 Guideline: Consider the Memory Block 2-2 Guideline: Implement External Conflict 2-3 Guideline: Customize Read-During-Write 2-3 Guideline: Consider Power-Up State and Memory 2-7 Guideline: Control Clocking to Reduce Power Memory 2-7 Embedded Memory Port 2-9 Embedded Memory 2-10 Embedded Memory Clocking 2-12 Clocking Modes for Each Memory 2-12 Asynchronous Clears in Clocking 2-13 Output Read Data in Simultaneous Clock Enables in Clocking Bit in Memory Enable in Embedded Memory 2-14 Byte Enable Controls in Memory 2-14 Data Byte 2-15 RAM Blocks 2-15 Memory Blocks Packed Mode Blocks Address Clock Enable 2-16 Embedded Memory Blocks in Cyclone V Devices Revision 2-18 TOC-2 Cyclone V Device Handbook Volume 1.

2 Device Interfaces and IntegrationAltera CorporationVariable Precision DSP Blocks in Cyclone V Operational Modes in Cyclone V 3-3 Operational 3-4 Internal Coefficient and 3-4 Chainout 3-4 Block 3-4 Input Register 3-7 Internal 3-8 Accumulator and Chainout 3-8 Systolic 3-9 Double Accumulation 3-9 Output Register 3-9 Operational Mode 3-10 Independent Multiplier 3-10 Independent Complex Multiplier 3-13 Multiplier Adder Sum 3-1518 x 18 Multiplication Summed with 36-Bit Input FIR 3-16 Variable Precision DSP Blocks in Cyclone V Devices Revision 3-18 Clock Networks and PLLs in Cyclone V 4-1 Clock 4-1 Clock Resources in Cyclone V 4-2 Types of Clock 4-4 Clock Sources Per of Clock 4-11 Clock Network 4-12 Clock Output 4-15 Clock Control 4-15 Clock Power 4-17 Clock Enable V 4-19 PLL Physical Counters in Cyclone V 4-20 PLL Locations in Cyclone V 4-21 PLL Migration Guidelines.

3 4-27 Fractional PLL 4-28 PLL 4-28 PLL External Clock I/O 4-29 PLL Control 4-30 Cyclone V Device Handbook Volume 1: Device Interfaces and IntegrationTOC-3 Altera CorporationClock Feedback Multiplication and 4-37 Programmable Phase 4-38 Programmable Duty Reconfiguration and Dynamic Phase 4-44 Clock Networks and PLLs in Cyclone V Devices Revision Features in Cyclone V Resources Per Package for Cyclone V Vertical Migration for Cyclone V Pin Migration 5-6I/O Standards Support in Cyclone V 5-6I/O Standards Support for FPGA I/O in Cyclone V 5-7I/O Standards Support for HPS I/O in Cyclone V 5-8I/O Standards Voltage Levels in Cyclone V 5-9 MultiVolt I/O Interface in Cyclone V 5-11I/O Design Guidelines for Cyclone V Voltage-Referenced and Non-Voltage-Referenced I/O and 5-13 LVDS Interface with External PLL 5-16 Guideline: Use the Same VCCPD for All I/O Banks in a : Ensure Compatible VCCIO and VCCPD Voltage in the Same 5-20 Guideline.

4 VREF Pin 5-20 Guideline: Observe Device Absolute Maximum Rating for V 5-20 Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement 5-21 Guideline: Pin Placement for General Purpose High-Speed 5-21I/O Banks Locations in Cyclone V Banks Groups in Cyclone V I/O Banks for Cyclone V E 5-24 Modular I/O Banks for Cyclone V GX 5-25 Modular I/O Banks for Cyclone V GT 5-26 Modular I/O Banks for Cyclone V SE 5-27 Modular I/O Banks for Cyclone V SX 5-27 Modular I/O Banks for Cyclone V ST 5-28I/O Element Structure in Cyclone V Buffer and Registers in Cyclone V 5-29 Programmable IOE Features in Cyclone V Current 5-33 Programmable Output Slew Rate IOE 5-35 Programmable Output Buffer 5-35 Programmable 5-35 Programmable Differential Output 5-36 Open-Drain 5-38 Pull-up 5-38On-Chip I/O Termination in Cyclone V V Device Handbook Volume 1.

5 Device Interfaces and IntegrationAltera CorporationRS OCT without Calibration in Cyclone V 5-39RS OCT with Calibration in Cyclone V OCT with Calibration in Cyclone V 5-43 Dynamic OCT in Cyclone V Input RD OCT in Cyclone V Calibration Block in Cyclone V 5-47 External I/O Termination for Cyclone V 5-50 Single-ended I/O 5-51 Differential I/O 5-53 Dedicated High-Speed Differential I/O 5-59 LVDS SERDES LVDS Buffers in Cyclone V LVDS Buffers in Cyclone V 5-71 Differential Transmitter in Cyclone V 5-71 Transmitter 5-71 Serializer Bypass for DDR and SDR 5-73 Differential Receiver in Cyclone V Blocks in Cyclone V 5-74 Receiver Mode in Cyclone V Clocking for Cyclone V 5-77 Differential I/O Termination for Cyclone V 5-77 Source-Synchronous Timing Data 5-78 Differential I/O Bit Channel-to-Channel 5-80 Receiver Skew Margin for LVDS Features in Cyclone V Devices Revision 5-83 External Memory Interfaces in Cyclone V 6-1 External Memory 6-1 HPS External Memory 6-2 Memory Interface Pin Support in Cyclone V 6-2 Guideline: Using DQ/DQS Bus Mode Pins for Cyclone V 6-3DQ/DQS Groups in Cyclone V 6-4DQ/DQS Groups in Cyclone V 6-6DQ/DQS Groups in Cyclone V 6-8DQ/DQS Groups in Cyclone V 6-10DQ/DQS Groups in Cyclone V Groups in Cyclone V 6-11 External Memory Interface Features in Cyclone V 6-12 UniPHY 6-12 External Memory Interface 6-13 DQS Phase-Shift Clock (PHYCLK) 6-21 DQS Logic 6-26 Dynamic OCT 6-29 Cyclone V Device Handbook Volume 1: Device Interfaces and IntegrationTOC-5 Altera CorporationIOE 6-30 Delay 6-31I/O and DQS Configuration 6-33 Hard Memory of the Hard Memory 6-34 Multi-Port Front End.

6 6-36 Bonding 6-37 Hard Memory Controller Width for Cyclone V Memory Controller Width for Cyclone V 6-40 Hard Memory Controller Width for Cyclone V 6-41 Hard Memory Controller Width for Cyclone V Memory Controller Width for Cyclone V 6-42 Hard Memory Controller Width for Cyclone V 6-43 External Memory Interfaces in Cyclone V Devices Revision 6-44 Configuration, Design Security, and Remote System Upgrades in Cyclone 7-1 Enhanced Configuration and Configuration via 7-1 MSEL Pin 7-3 Power 7-6 Configuration Error 7-6 User 7-6 Configuration Timing Configuration 7-7AS Configuration 7-9PS Configuration 7-10 Device Configuration Standards and Drive Strength for Configuration Pin Options in the intel Quartus Prime Passive Parallel Passive Parallel Single- Device 7-14 Fast Passive Parallel Multi- Device 7-15 Transmitting Configuration 7-17 Active Serial 7-18 DATA Clock (DCLK).

7 7-18 Active Serial Single- Device 7-18 Active Serial Multi- Device 7-20 Estimating the Active Serial Configuration 7-21 Using EPCS and EPCQ EPCS and EPCQ 7-22 Trace Length and Loading 7-22 Programming EPCS and EPCQ 7-22 Passive Serial 7-26 Passive Serial Single- Device Configuration Using an External 7-27 TOC-6 Cyclone V Device Handbook Volume 1: Device Interfaces and IntegrationAltera CorporationPassive Serial Single- Device Configuration Using an Altera Download 7-27 Passive Serial Multi- Device 7-31 JTAG Single- Device 7-32 JTAG Multi- Device 7-33 CONFIG_IO JTAG 7-34 Configuration Data Compression Before Design 7-35 Enabling Compression After Design Compression in Multi- Device 7-35 Remote System 7-37 Configuration Sequence in the Remote Update 7-38 Remote System Upgrade 7-38 Enabling Remote System Upgrade 7-39 Remote System Upgrade 7-40 Remote System Upgrade State 7-41 User Watchdog 7-41 Design Unique Chip ID IP Secure Key 7-43 Security 7-44 Design Security Implementation 7-45 Configuration, Design Security.

8 And Remote System Upgrades in Cyclone V Devices 7-46 SEU Mitigation for Cyclone V 8-1 Error Detection 8-1 Configuration Error Mode Error 8-2 Internal 8-2 Minimum EMR Update Detection 8-3 CRC Calculation Time For Entire 8-4 Using Error Detection Features in User Error 8-5 CRC_ERROR 8-6 Error Detection Detection 8-8 Testing the Error Detection 8-9 SEU Mitigation for Cyclone V Devices Document Revision Boundary-Scan Testing in Cyclone V Operation Control .. 9-1 IDCODE ..9-1 Cyclone V Device Handbook Volume 1: Device Interfaces and IntegrationTOC-7 Altera CorporationSupported JTAG Instruction ..9-3 JTAG Secure Mode ..9-7 JTAG Private Instruction .. 9-7I/O Voltage for JTAG Operation .. 9-8 Performing BST .. 9-8 Enabling and Disabling IEEE Std. BST Circuitry ..9-9 Guidelines for IEEE Std. Boundary-Scan 9-10 IEEE Std. Boundary-Scan Register.

9 9-10 Boundary-Scan Cells of a Cyclone V Device I/O 9-11 JTAG Boundary-Scan Testing inCyclone V Devices Revision 9-13 Power Management in Cyclone V 10-1 Dynamic Power 10-1 Hot-Socketing 10-2 Power-Up Sequence Recommendation for Cyclone V 10-4 Power-On Reset Supplies Monitored and Not Monitored by the POR Management in Cyclone V Devices Revision 10-8 TOC-8 Cyclone V Device Handbook Volume 1: Device Interfaces and IntegrationAltera CorporationLogic Array Blocks and Adaptive Logic Modulesin Cyclone V FeedbackThis chapter describes the features of the logic array block (LAB) in the Cyclone V core LAB is composed of basic building blocks known as adaptive logic modules (ALMs) that you canconfigure to implement logic functions, arithmetic functions, and register can use a quarter of the available LABs in the Cyclone V devices as a memory LAB (MLAB).

10 The intel Quartus Prime software and other supported third-party synthesis tools, in conjunction withparameterized functions such as the library of parameterized modules (LPM), automatically choose theappropriate mode for common functions such as counters, adders, subtractors, and arithmetic chapter contains the following sections: LAB ALM Operating ModesRelated InformationCyclone V Device Handbook : Known IssuesLists the planned updates to the Cyclone V Device Handbook LABs are configurable logic blocks that consist of a group of logic resources. Each LAB containsdedicated logic for driving control signals to its is a superset of the LAB and includes all the LAB Corporation. All rights reserved. intel , the intel logo, Altera, Arria, Cyclone , Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks ofIntel Corporation or its subsidiaries in the and/or other countries.


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