1 ENC28J60 . stand - alone ethernet controller with SPI interface ethernet controller Features Operational IEEE Compatible ethernet controller Six Interrupt Sources and One Interrupt Output Pin Fully Compatible with 10/100/1000 Base-T Networks 25 MHz Clock Input Requirement Integrated MAC and 10 Base-T PHY Clock Out Pin with Programmable Prescaler Supports One 10 Base-T Port with Automatic Operating Voltage of to ( typical). Polarity Detection and Correction 5V Tolerant Inputs Supports Full and Half-Duplex modes Temperature Range: -40 C to +85 C Industrial, 0 C to +70 C Commercial (SSOP only). Programmable Automatic Retransmit on Collision 28-Pin SPDIP, SSOP, SOIC, QFN Packages Programmable Padding and CRC Generation Programmable Automatic Rejection of Erroneous Package Types Packets SPI interface with Clock Speeds up to 20 MHz 28-Pin SPDIP, SSOP, SOIC. VCAP 1 28 VDD. Buffer VSS 2 27 LEDA. CLKOUT 3 26 LEDB.
2 8-Kbyte Transmit/Receive Packet Dual Port SRAM INT 4 25 VDDOSC. NC(1) 5 24 OSC2. ENC28J60 . Configurable Transmit/Receive Buffer Size SO 6 23 OSC1. Hardware Managed Circular Receive FIFO SI 7 22 VSSOSC. Byte-Wide Random and Sequential Access with SCK 8 21 VSSPLL. CS 9 20 VDDPLL. Auto-Increment RESET 10 19 VDDRX. Internal DMA for Fast data Movement VSSRX 11 18 VSSTX. Hardware Assisted Checksum Calculation for TPIN- 12 17 TPOUT+. TPIN+ 13 16 TPOUT- Various Network Protocols RBIAS 14 15 VDDTX. Medium Access controller (MAC). Features 28-Pin QFN(2). CLKOUT. LEDA. LEDB. VCAP. Supports Unicast, Multicast and Broadcast VDD. VSS. INT. Packets Programmable Receive Packet Filtering and Wake-up Host on Logical AND or OR of the Following: 28 27 26 25 24 23 22. - Unicast destination address NC(1) 1 21 VDDOSC. - Multicast address SO 2 20 OSC2. - Broadcast address SI 3 19 OSC1. SCK 4 ENC28J60 18 VSSOSC. - Magic Packet 17.
3 CS 5 VSSPLL. - Group destination addresses as defined by RESET 6 16 VDDPLL. 64-bit Hash Table VSSRX 7 15 VDDRX. - Programmable Pattern Matching of up to 8 9 10 11 12 13 14. 64 bytes at user-defined offset Physical Layer (PHY) Features TPIN- TPOUT- TPIN+. TPOUT+. RBIAS. VDDTX. VSSTX. Loopback mode Two Programmable LED Outputs for LINK, TX, Note 1: Reserved pin; always leave disconnected. RX, Collision and Full/Half-Duplex Status 2: The back pad on QFN devices should be connected to Vss. 2006-2012 Microchip Technology Inc.. DS39662E-page 1. ENC28J60 . Table of Contents Overview .. 3. External Connections .. 5. Memory Organization .. 11. serial peripheral interface (SPI).. 25. ethernet Overview .. 31. 33. Transmitting and Receiving Packets .. 39. Receive 47. Duplex Mode Configuration and 53. Flow Control .. 55. Reset .. 59. Interrupts .. 63. Direct Memory Access controller .. 71. Power-Down .. 73. Built-in Self-Test controller .
4 75. Electrical Characteristics .. 79. Packaging 83. Appendix A: Revision 93. The Microchip Web Site .. 95. Customer Change Notification Service .. 95. Customer Support .. 95. Reader Response .. 96. Product Identification 99. TO OUR VALUED CUSTOMERS. It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at or fax the Reader Response Form in the back of this data Sheet to (480) 792-4150. We welcome your feedback. Most Current data Sheet To obtain the most up-to-date version of this data Sheet , please register at our Worldwide Web site at: You can determine the version of a data Sheet by examining its literature number found on the bottom outside corner of any page.
5 The last character of the literature number is the version number, ( , DS30000A is version A of document DS30000). Errata An errata Sheet , describing minor operational differences from the data Sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata Sheet . The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata Sheet exists for a particular device, please check with one of the following: Microchip 's Worldwide Web site; Your local Microchip sales office (see last page). When contacting a sales office, please specify which device, revision of silicon and data Sheet (include literature number) you are using. Customer Notification System Register on our web site at to receive the most current information on all of our products. DS39662E-page 2 . 2006-2012 Microchip Technology Inc.
6 ENC28J60 . OVERVIEW The ENC28J60 consists of seven major functional blocks: The ENC28J60 is a stand - alone ethernet controller 1. An SPI interface that serves as a communica- with an industry standard serial peripheral interface tion channel between the host controller and the (SPI). It is designed to serve as an ethernet network ENC28J60 . interface for any controller equipped with SPI. 2. Control registers which are used to control and The ENC28J60 meets all of the IEEE specifica- monitor the ENC28J60 . tions. It incorporates a number of packet filtering 3. A dual port RAM buffer for received and schemes to limit incoming packets. It also provides an transmitted data packets. internal DMA module for fast data throughput and hard- ware assisted checksum calculation, which is used in 4. An arbiter to control the access to the RAM buf- various network protocols. Communication with the fer when requests are made from DMA, transmit host controller is implemented via an interrupt pin and and receive blocks.
7 The SPI, with clock rates of up to 20 MHz. Two 5. The bus interface that interprets data and dedicated pins are used for LED link and network commands received via the SPI interface . activity indication. 6. The MAC (Medium Access Control) module that A simple block diagram of the ENC28J60 is shown in implements IEEE compliant MAC logic. Figure 1-1. A typical application circuit using the device 7. The PHY (Physical Layer) module that encodes is shown in Figure 1-2. With the ENC28J60 , two pulse and decodes the analog data that is present on transformers and a few passive components are all that the twisted-pair interface . are required to connect a microcontroller to an ethernet The device also contains other support blocks, such as network. the oscillator, on-chip voltage regulator, level translators to provide 5V tolerant I/Os and system control logic. FIGURE 1-1: ENC28J60 BLOCK DIAGRAM. LEDA. Buffer RX LEDB.
8 8 Kbytes Dual Port RAM MAC. RXBM. TPOUT+. RXF (Filter). MII TX TPOUT- ch0 interface CLKOUT DMA &. Control ch0. Arbiter Checksum Registers PHY. TPIN+. ch1 TX. ch1 RX TPIN- TXBM. INT. Flow Control Bus interface MIIM RBIAS. interface Host interface CS(1). SI(1) OSC1. SPI 25 MHz SO Power-on Voltage OSC2. System Control Oscillator Reset Regulator SCK(1). RESET(1) VCAP. Note 1: These pins are 5V tolerant. 2006-2012 Microchip Technology Inc.. DS39662E-page 3. ENC28J60 . FIGURE 1-2: TYPICAL ENC28J60 BASED interface . MCU ENC28J60 TPIN+/- CS RJ45. I/O. SI TPOUT+/- SDO. SO. SDI ethernet . SCK. SCK TX/RX TRANSFORMER. Buffer MAC PHY. INT LEDA. INTX. LEDB. TABLE 1-1: PINOUT I/O DESCRIPTIONS. Pin Number Pin Buffer Pin Name SPDIP, Description QFN Type Type SOIC, SSOP. VCAP 1 25 P output from internal regulator. A low Equivalent Series Resistance (ESR). capacitor, with a typical value of 10 F and a minimum value of 1 F to ground, must be placed on this pin.
9 VSS 2 26 P Ground reference. CLKOUT 3 27 O Programmable clock output pin.(1). INT 4 28 O INT interrupt output pin.(2). NC 5 1 O Reserved function; always leave unconnected. SO 6 2 O data out pin for SPI interface .(2). SI 7 3 I ST data in pin for SPI interface .(3). SCK 8 4 I ST Clock in pin for SPI interface .(3). CS 9 5 I ST Chip select input pin for SPI interface .(3,4). RESET 10 6 I ST Active-low device Reset input.(3,4). VSSRX 11 7 P Ground reference for PHY RX. TPIN- 12 8 I ANA Differential signal input. TPIN+ 13 9 I ANA Differential signal input. RBIAS 14 10 I ANA Bias current pin for PHY. Must be tied to ground via a resistor (refer to Section Magnetics, Termination and Other External Components . for details). VDDTX 15 11 P Positive supply for PHY TX. TPOUT- 16 12 O Differential signal output. TPOUT+ 17 13 O Differential signal output. VSSTX 18 14 P Ground reference for PHY TX. VDDRX 19 15 P Positive supply for PHY RX.
10 VDDPLL 20 16 P Positive supply for PHY PLL. VSSPLL 21 17 P Ground reference for PHY PLL. VSSOSC 22 18 P Ground reference for oscillator. OSC1 23 19 I ANA Oscillator input. OSC2 24 20 O Oscillator output. VDDOSC 25 21 P Positive supply for oscillator. LEDB 26 22 O LEDB driver pin.(5). LEDA 27 23 O LEDA driver pin.(5). VDD 28 24 P Positive supply. Legend: I = Input, O = Output, P = Power, ANA = Analog Signal Input, ST = Schmitt Trigger Note 1: Pins have a maximum current capacity of 8 mA. 2: Pins have a maximum current capacity of 4 mA. 3: Pins are 5V tolerant. 4: Pins have an internal weak pull-up to VDD. 5: Pins have a maximum current capacity of 12 mA. DS39662E-page 4 . 2006-2012 Microchip Technology Inc. ENC28J60 . EXTERNAL CONNECTIONS Oscillator Start-up Timer The ENC28J60 contains an Oscillator Start-up Timer Oscillator (OST) to ensure that the oscillator and integrated PHY. The ENC28J60 is designed to operate at 25 MHz with a have stabilized before use.