Flip-Flops and Sequential Circuit Design

1 Flip-Flops and Sequential Circuit DesignECE 152A Winter 2012 February 13, 2012 ECE 152A -Digital Design Principles2 Reading Assignment Brown and Vranesic 7 Flip-Flops , Registers, Counters and a Simple Processor T Flip-Flop Configurable Flip-Flops JK Flip-Flop Summary of Terminology Registers Shift Register Parallel-Access Shift RegisterFebruary 13, 2012 ECE 152A -Digital Design Principles3 Reading Assignment Brown and Vranesic(cont) 7 Flip-Flops , Registers, Counters and a Simple Processor (cont) Counters Asynchronous Counters Synchronous Counters Counters with Parallel Load Reset SynchronizationFebruary 13, 2012 ECE 152A -Digital Design Principles4 Reading Assignment Brown and Vranesic(cont) 7 Flip-Flops , Registers, Counters and a Simple Processor (cont)

2 Other Types of Counters BCD Counter Ring Counter Johnson Counter Remarks on Counter DesignFebruary 13, 2012 ECE 152A -Digital Design Principles5 Reading Assignment Brown and Vranesic(cont) 8 Synchronous Sequential Circuits Basic Design Steps State Diagram State Table State Assignment Choice of Flip-Flops and Derivation of Next-State and Output Expressions Timing Diagram Summary of Design StepsFebruary 13, 2012 ECE 152A -Digital Design Principles6 Reading Assignment Brown and Vranesic(cont) 8 Synchronous Sequential Circuits (cont)

3 State-Assignment Problem One-Hot Encoding Design of a Counter Using the Sequential Circuit Approach State Diagram and State Table for Modulo-8 Counter State Assignment Implementation Using D-Type Flip-Flops Implementation Using JK-Type Flip-Flops Example A Different CounterFebruary 13, 2012 ECE 152A -Digital Design Principles7 Reading Assignment Roth 11 Latches and Flip-Flops S-R Flip-Flop J-K Flip-Flop T Flip-Flop Flip-Flops with Additional Inputs Summary 12 Registers and Counters Counter Design Using S-R and J-K Flip-Flops Derivation of Flip-Flop Input Equations SummaryFebruary 13, 2012 ECE 152A -Digital Design Principles8 The JK Flip-Flop Allows J = K = 1 condition Implemented with a gated SR latch and feedback of Q and Q* Q toggles (Q+= Q )

4 On J = K = 1 February 13, 2012 ECE 152A -Digital Design Principles9 The JK Flip-Flop (cont) Characteristic table and equation Karnaugh map of characteristic table Characteristic equation Q+= JQ + K QFebruary 13, 2012 ECE 152A -Digital Design Principles10 The JK Flip-Flop (cont) Implementation using a D flip-flop Characteristic Function at D inputFebruary 13, 2012 ECE 152A -Digital Design Principles11 The JK Flip-Flop State table1110(Q+)001110001101JK = 00PS (Q)NSFebruary 13, 2012 ECE 152A -Digital Design Principles12 The JK Flip-Flop State diagram10JK = X1JK = 1 XJK = 0 XJK = X0 February 13, 2012 ECE 152A -Digital Design Principles13 The JK Flip-Flop With clock circuitry and timing Positive edge triggered JK flip-flopFebruary 13, 2012 ECE 152A -Digital Design Principles14 The Master Slave JK Flip-Flop Master Slave JK Flip-Flop Rising edge triggered note CLK inverted to masterFebruary 13.

5 2012 ECE 152A -Digital Design Principles15 The Master Slave JK Flip-Flop Master Slave JK Flip-Flop Falling edge triggered note CLK (CP) inverted to slaveFebruary 13, 2012 ECE 152A -Digital Design Principles16 The Master Slave JK Flip-Flop Master active on CLK = 1 Slave active on CLK = 0 Latch data in master on CLK = 1 Transfer data to slave (output) on CLK = 0 Timing Diagram Initial Conditions CLK = 0, J = 1, K = 0, Y = 0, Q = 0 February 13, 2012 ECE 152A -Digital Design Principles17 The Master Slave JK Flip-Flop Timing DiagramFebruary 13, 2012 ECE 152A -Digital Design Principles18 The JK Flip-Flop (cont) What happens if J = K = 1 for an indefinite period of time ( , much greater than clock period)?

6 Output oscillates at the frequency of the clock Divide by two counterFebruary 13, 2012 ECE 152A -Digital Design Principles19 The T (Toggle or Trigger) Flip-Flop Connect J and K inputs together Combined input T Characteristic TableCharacteristicEquationTimingDiagram February 13, 2012 ECE 152A -Digital Design Principles20 The T Flip-Flop State Table011100T=1T = 0PS (Q)NS (Q+)February 13, 2012 ECE 152A -Digital Design Principles21 The T Flip-Flop State Diagram10T = 1T = 1T = 0T = 0 February 13, 2012 ECE 152A -Digital Design Principles22 The T Flip-Flop (from JK/D)

7 Q+= JQ + K QQ+= T Q + TQ = T XOR QFebruary 13, 2012 ECE 152A -Digital Design Principles23 Counter Design with T Flip-Flops 3 bit binary counter Design example State refers to Q s of Flip-Flops 3 bits, 8 states Decimal 0 through 7 No inputs Transition on every clock edge , state changes on every clock edge Assume clocked, synchronous flip-flopsFebruary 13, 2012 ECE 152A -Digital Design Principles24 Counter Design with T Flip-Flops State Diagram001100011010111000110101 February 13, 2012 ECE 152A -Digital Design Principles25 Counter Design with T Flip-Flops State table00011111101101110110100100111011001 0010100100000C+B+A+CBANSPSF ebruary 13, 2012 ECE 152A -Digital Design Principles26 Counter Design with T Flip-Flops Next State MapsBCA00010111101111 BCA0001011110 BCA000101111011111111A+= AB + AC + A BC = DAB+= B C + BC = DBC+= C = DCFebruary 13, 2012 ECE 152A -Digital Design Principles27 Counter Design with T Flip-Flops Using D Flip-Flops .

8 Inputs are derived directly from next state maps D = Q+ Using T flip flops Excitation table (used for Design ) T = Q XOR Q+ Need to find inputs to T Flip-Flops Mapping state changes Q Q+ requires T = ?February 13, 2012 ECE 152A -Digital Design Principles28 Counter Design with T Flip-Flops T Flip-Flop Excitation Table T = Q XOR Q+011101110000TQ+QFebruary 13, 2012 ECE 152A -Digital Design Principles29 Counter Design with T Flip-Flops State Variable A TA= A+(XOR) ABCA0001A=0A=11110A+=1 BCA0001011110T=1T=1A+=1A+=1A+=1A+= AB + AC + A BC = DATA= BCFebruary 13, 2012 ECE 152A -Digital Design Principles30 Counter Design with T Flip-Flops State Variable B TB= B+(XOR)

9 BBCA0001011110B+=1 BCA0001011110T=1T=1B+=1B+=1B+=1B+= B C + BC = DBTB= CB=0B=1T=1T=1 February 13, 2012 ECE 152A -Digital Design Principles31 Counter Design with T Flip-Flops State Variable C TC= C+(XOR) CBCA0001011110C+=1 BCA0001011110T=1T=1C+=1C+=1C+=1C+= C = DCTC= 1T=1T=1T=1T=1T=1T=1C=1C=0C=0 February 13, 2012 ECE 152A -Digital Design Principles32 Counter Design with T Flip-Flops Implement Design using T Flip-Flops with asynchronous preset and clear Asynchronous preset (PRN) and clear (CLRN) override clock and other inputs Preset : Q 1, Clear.

10 Q 0 Used to initialize system (all Flip-Flops ) to known state Bubbles indicate low true or active low TA = BC, TB = C, TC = 1 February 13, 2012 ECE 152A -Digital Design Principles33 Counter Design with T Flip-Flops SchematicFebruary 13, 2012 ECE 152A -Digital Design Principles34 Counter Design with T Flip-Flops Timing Diagram QA toggles when B = C = 1 QB toggles when C = 1 QC toggles on every clock edgeFebruary 13, 2012 ECE 152A -Digital Design Principles35 Counter Design with JK Flip-Flops State Diagram100111011000010 February 13.