Transistor Technologies for High Efficiency and Linearity

1 Transistor Technologies for High Efficiency and Linearity HEMT Requirements for Transistors in Power Amplifiers Iout Vout Vmin Nonlinear FET Iout Vout Vmin Nonlinear HBT High microwave gain Low on-resistance & low knee voltage High power density High voltage capability Linearity Ease of matching Ease of biasing Adequate heatsinking Low cost (high yield) Reliability & ruggedness Stability Central Concern for Transistors in ECE265C What is highest voltage that can be maintained? What is highest current that can be delivered? What is highest power that can be withstood? Safe Operating Area for Transistors I V Imax On-state breakdown voltage Off-state breakdown voltage Maximum power dissipation Imax depends on device size Maximum power dissipation depends on size and duty cycle - worse for CW tone than for high PAR signals Tradeoff of Breakdown Voltage and ft To avoid breakdown, generally must limit peak electric field to below a critical value, Eb To achieve high voltage, one can design the high field region to be long: Vbk= Eb *wc The large wc tends to increase transit time for carriers, resulting in low ft: Ttr>wc/vsat, Ft=1/(2p Ttr) The product of Vbk and ft tends to be independent of wc.

2 Vbk*ft <= Eb * vsat / 2 p CMOS scaling through Moore s Law acts to drive up ft, but it drives down Vbk at the same time. Ft=1/(2pTtr) Ttr=Wc/vsat (or Wc/vsat) BV=1/2 Eb Wc (or Eb Wc) BV*ft = Eb Wc * 1/2p vsat /Wc BV*ft ~ 1/2p Eb *vsat Speed-Voltage Tradeoff in Transistors Channel or BC depletion region Drain or collector Source or base Wc Ttr Johnson Figure-of-merit Eb: breakdown electric field Transistor Size Need to pick device large enough to support Imax Not necessarily well described in SPICE models For bipolars: Ic/Aemitter = Jc < 2-5 mA/um2 for Si < mA/um2 for GaAs For FETs.

3 Id/ Wg < A/mm for CMOS A/mm for LDMOS A/mm for pHEMT A/mm for GaN Thermal Effects in Power Transistors Burnout (melting of portions of device, rapid diffusion of defects, excess stress, etc) Degradation Thermal runaway in bipolar transistors Decreased performance: reduced Iout, lower ft, etc Thermally induced distortion & memory effect Difference between cw and short-time ac characteristics Negative Output Conductance due to heating Basics of Thermal Circuits Thermal Resistance of Transistor Main contribution is often Rth to back of chip 02468101214161820 DiamondSiCCopperGoldSiliconGaNInPGaAsSiO 2 TeflonK(W/cmK) 20 Thermal Resistance Calculations Using 3D Structure Simulators (solve Laplace s equation)

4 Ansys, comsol, sentaurus, etc InP HBT CMOS SOI Thermal Resistance Estimate 1 Rth for section near device is >> Rth at bottom Thermal Resistance Estimate 2 How To Decrease Thermal Resistance Thin substrates Thermal Vias Heat Spreaders Flip-chip bonding (? sometimes) FETs for Power Amplifiers CMOS LDMOS (Laterally Diffused MOS) MESFET HEMT pHEMT Si GaAs InP GaN Different Flavors of FET MOSFET MESFET HEMT Limits in CMOS Transistors Limits on Ids: maximum channel charge is limited by gate oxide field: qNsmax~ eox Eoxmax Oxide breakdown: typically occurs at 10MV/cm=> 1V for every 10A of gate oxide Gate-channel breakdown will occur at source or drain, wherever field is highest.

5 There are slow oxide breakdown mechanisms too (time-dependent dielectric breakdown) Avalanche breakdown in channel at high VDS values Oxide charging: when operated at high Vds, electrons are injected into the gate oxide, creating trapped charge which shifts device threshold (hot carrier injection) Hot Electron Generation Source Channel Drain High electric field - - + - High Voltage Breakdown Mechanism of MOS Transistor Impact ionization at drain edge of gate What happens to holes generated by impact ionization? They flow to the substrate and to the source. They cause some extra current due to body effect. They can be measured as substrate or well current.

6 Moderate electric field , ACMOS Id-Vds curve (generic) SOI effects Gate Source Drain Impact ionization Bipolar injection current N+ N+ p Parasitic bipolar Transistor Fed by impact ionization Causes excess Id, lower BV "snapback" Lightly Doped Drain Structure (LDD) To Minimize Hot Electron Effects Minimize electric field near drain Differential Topology Double the available voltage swing Even-order harmonic suppression Double the frequency of current injection into substrate Reduce the potential for LO-pulling The tail current source is removed from the standard differential pair (this is a quasi-differential structure) DC current set by the biasing of input devices Max.

7 Current set by the input voltage swing May require differential to single-ended output conversion (balun) Technique to improve CMOS PAs: Cascode Structure Generally used in Op-Amps and other analog designs Increase the small-signal output resistance Reduce the Miller effect In the case of RF PA, isolate the input and output nodes Reduce the impact of oxide breakdown On the cascode device, Vox(max) = Vout(max) - Vbias On the bottom device, Vox(max) = Vcasc - Vin = Vbias - Vt - Vin(min) Technique to improve CMOS PAs: Id-Vds Characteristics of Cascode (m2)ID(m4)0A100mA200mA300mAId-Vds for Cascode: Higher Ron Lower Idmax Body effect on top FET Higher Vmin decreases Efficiency Stacked-FET Structure time, nsec Vgs1, V Vds1, V Vgs2 Vds2 Vgs3 Vds3 Vds, i Vgs, i Vds and Vgs swing of each FET All FETs are operating in the safe region Stacked-FET Structure time, nsec Vgs1, V Vds1, V Vgs2 Vds2 Vgs3 Vds3 Vds, i Vgs.

8 I Vds and Vgs swing of each FET All FETs are operating in the safe region Stacked-FET Structure C2 Zs2= Ropt Zs3= 2 Ropt 3 Ropt C3 m g C gs C s Z 1 2 1 2 + @ Zs2 2 Tailor swing at each drain and gate by proper selection of gate capacitor Id~gm Vgs ~gm Vt C2/(C2+Cgs) Stacked FET Approach for CMOS PAs -20-15-10-505107580859095100105110S - parameters (dB) Freq (GHz) 50 mW Psat at 90 GHz In 45 nm CMOS SOI Works well at least up to 90 GHz !!! Jefy Jayamon (UCSD) Power Combining with Distributed Active Transformers Aoki, Kee, Hajimiri and Rutledge (Caltech) CMOS Amplifier with On-Chip Transformer Grain of salt LDMOS Drain Wsi / Poly Gate Source P+ Sinker P-epi P+ Enhancement NHV N+ N+ PHV Metal LDMOS Lightly doped n - type LDMOS Model: Approach 1 D.

9 Klassen et al LDMOS Transistors are current workhorses for Basestation PAs LDMOS prices Historically $1 / peak Watt (Basestation PA 200W peak)=> $200 With present heavy competition $ / peak Watt GaAs MESFET GaAs-based Metal-Schottky FET Low Ron, high ft, high BV High gm compared with Si Microwave IC capability (S-I substrate) Typically depletion-mode (negative supply needed) gm varies with Vin Rout moderate, varies with f and Vds Gate conducts at high bias rectifies input signal Vgs gm Vds Id Vt Vgon Channel Charge in GaAs MESFETs If reverse bias on Schottky gate is increased, Channel becomes more depleted, channel charge decreases Channel charge Q ~ q Nd (a-w) w=sqrt[2e(V+Vbi)/qNd] X=w Vgs => I-V curves similar to MOSFET Gradual Channel Approx.

10 Id=1/2 CinmW/L(Vgs-Vt)2 in saturation region Typically depletion mode Q Vt Vbi DC vs Pulsed Id-Vds Characteristics of GaAs FET Idealized Current Transient for III-V FET How To Increase Breakdown Voltage in III-V FETs Multiple gate recesses particularly on drain side Just like "drain extension" MOSFET Field plate Modulates electric field at drain edge of gate Just like LDMOS HEMT GaAs-based High Electron Mobility FET Low Ron, high ft, high BV Very high gm Microwave IC capability (S-I substrate) Typically depletion-mode (negative supply needed) gm varies only slightly with Vin Rout high, can be controlled Gate conducts at high bias rectifies input signal Vgs gm Vds Id HEMT MOSFET GaAs Pseudomorphic HEMT (pHEMT) Ultrahigh Speed Transistors Gate length 25 nm InGaAs channel with 70% In on InP substrate to 1 mm Gate WidthIds (A)Vds (V)101520253001020304050607080-505101520 25 Load-Pull for PAE TuningGain_PAE tuningPAE_PAE tuningGain (dB)PAE (%)Pout (dBm) to 1 mm Gate WidthGm (S)Vgs (V)