High- performance EPLD

1 1 TQFPTop View12345678910113332313029282726252423I /OI/OI/OGNDI/OI/OI/OI/OVCCI/OI/OI/OI/OI/ OI/OVCCI/OI/OI/OI/OGNDI/O444342414039383 73635341213141516171819202122I/OI/OI/OI/ OGNDVCCI/OI/OI/OI/OI/OI/OI/OI/O/PDVCCOE2 /IGCLR/IOE1/ICLK/IGNDI/OI/OPLCCTop View789101112131415161739383736353433323 13029I/OI/OI/OGNDI/OI/OI/OI/OVCCI/OI/OI/ OI/OI/OI/OVCCI/OI/OI/OI/OGNDI/O654321444 34241401819202122232425262728I/OI/OI/OI/ OGNDVCCI/OI/OI/OI/OI/OI/OI/OI/O/PDVCCOE2 /IGCLR/IOE1/ICLK/IGNDI/OI/OPin ConfigurationsPinNameFunctionCLKC lockILogic InputsI/OBi-directional BuffersGCLRR egister Reset (active low)OE1, OE2 Output Enable (active low)VCC+5V SupplyPDPower-down (active high)Features High- density, High- performance Electrically-erasable Complex Programmable Logic Device 44-pin, 32 I/O CPLD ns Maximum Pin-to-pin Delay Registered Operation Up to 125 MHz Fully Connected Input and Feedback Logic Array Backward Compatibility with ATF1500/L Software and Hardware Flexible Logic Macrocell D/T/Latch Configurable flip - flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Advanced Power Management Features Automatic 3 mA Standby (ATF1500AL)

2 Pin-controlled 10 mA Standby Mode Programmable Pin-keeper Inputs and I/Os Available in Commercial and Industrial Temperature Ranges Available in 44-lead PLCC and TQFP Packages Advanced Flash Technology 100% Tested Completely Reprogrammable 100 Program/Erase Cycles 20 Year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity Supported by Popular third-arty Tools Security Fuse Feature Pin-compatible with the Most Commonly Used Devices Green (Pb/Halide-fee/RoHS Compliant) Package Options DescriptionThe ATF1500A is a High- performance , High- density complex PLD. Built on anadvanced Flash technology, it has maximum pin-to-pin delays of ns and supportssequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and upto 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic ATF1500A s global input and feedback architecture simplifies logic placementand eliminates pinout changes due to design performance EPLDATF1500 AATF1500 ALRev.

3 0759F 6/05(continued)ATF1500A(L)2 Functional Logic Diagram(1) connecting macrocells indicate direction and groupings of CASIN/CASOUT data ATF1500A has 32 bi-directional I/O pins and four dedi-cated input pins. Each dedicated input pin can also serveas a global control signal: register clock, register reset oroutput enable. Each of these control signals can beselected for use individually within each of the 32 logic macrocells generates a buried feed-back, which goes to the global bus. Each input and I/O pinalso feeds into the global bus. Because of this global bus-ing, each of these signals is always available to all 32 mac-rocells in the (L)3 Each macrocell also generates a foldback logic term, whichgoes to a regional bus. All signals within a regional bus areconnected to all 16 macrocells within the logic between macrocells in the ATF1500A allowsfast, efficient generation of complex logic functions.

4 TheATF1500A contains four such logic chains, each capable ofcreating sum term logic with a fan-in of up to 40 productterms. Bus-friendly Pin-keeper Input and I/O sAll Input and I/O pins on the ATF1500A have programma-ble pin-keeper circuits. If activated, when any pin is drivenhigh or low and then subsequently left floating, it will stay atthat previous high or low level. This circuitry prevents unused Input and I/O lines fromfloating to intermediate voltage levels, which causesunnecessary power consumption and system noise. Thekeeper circuits eliminate the need for external pull-up resis-tors and eliminate their DC power consumption. Pin-keeper circuits can be disabled. Programming is con-trolled in the logic design file. Once the pin-keeper circuitsare disabled, normal termination procedures are requiredfor unused inputs and ManagementThe ATF1500A has several built-in speed and power man-agement features.

5 The ATF1500A contains circuitry thatautomatically puts the device into a low-power standbymode when no logic transitions are occurring. This not onlyreduces power consumption during inactive periods, butalso provides proportional power savings for most applica-tions running at system speeds below 10 ATF1500As also have an optional pin-controlled power-down mode. In this mode, current drops to below 10 the power-down option is selected, the PD pin isused to power-down the part. The power-down option isselected in the design source file. When enabled, thedevice goes into power-down when the PD pin is high. Inthe power-down mode, all internal logic signals are latchedand held, as are any enabled outputs. All pin transitions areignored until the PD is brought low. When the power-downfeature is enabled, the PD cannot be used as a logic inputor output. However, the PD pin s macrocell may stillbe used to generate buried foldback and cascadelogic output also has individual slew rate control.

6 This maybe used to reduce system noise by slowing down outputsthat do not need to operate at maximum speed. Outputsdefault to slow switching, and may be specified as fastswitching in the design file. Design Software SupportATF1500A designs are supported by several third-partytools. Automated fitters allow logic synthesis using a varietyof High- level description languages and DiagramI/O Diagram100 KVCCESDPROTECTIONCIRCUITINPUTPROGRAMMABL EOPTION100 KVCCVCCDATAOEI/OPROGRAMMABLEOPTIONATF150 0A(L)4 ATF1500A(L) MacrocellATF1500A MacrocellThe ATF1500A macrocell is flexible enough to supporthighly-complex logic functions operating at high speed. Themacrocell consists of five sections: product terms and prod-uct term select multiplexer, OR/XOR/CASCADE logic, aflip-flop, output select and enable, and logic array Terms and Select MuxEach ATF1500A macrocell has five product terms. Eachproduct term receives as its inputs all signals from both theglobal bus and regional bus.

7 The product term select multiplexer (PTMUX) allocates thefive product terms as needed to the macrocell logic gatesand control signals. The PTMUX programming is deter-mined by the design compiler that selects the optimummacrocell LogicThe ATF1500A macrocell s OR/XOR/CASCADE logicstructure is designed to efficiently support all types of a single macrocell, all the product terms can berouted to the OR gate, creating a five input AND/OR sumterm. With the addition of the CASIN from neighboringmacrocells, this can be expanded to as many as 40 productterms with little small additional macrocell s XOR gate allows efficient implementationof compare and arithmetic functions. One input to the XORcomes from the OR sum term. The other XOR input can bea product term or a fixed high or low level. For combinato-rial outputs, the fixed level input allows output polarityselection. For registered functions, the fixed levels allow DeMorgan minimization of the product terms.

8 The XOR gate isalso used to emulate T-type ATF1500A s flip -flop has very flexible data and controlfunctions. The data input can come from either the XORgate or from a separate product term. Selecting the sepa-rate product term allows creation of a buried registeredfeedback within a combinatorial output (L)5In addition to D, T, JK and SR operation, the flip -flop canalso be configured as a flow-through latch. In this mode,data passes through when the clock is high and is latchedwhen the clock is low. The clock itself can be either the global CLK pin or an indi-vidual product term. The flip -flop changes state on theclock s rising edge. When the CLK pin is used as the clock,one of the macrocell product terms can be selected as aclock enable. When the clock enable function is active andthe enable signal (product term) is low, all clock edges flip -flop s asynchronous reset signal (AR) can be eitherthe pin global clear (GCLR), a product term, or always can also be a logic OR of GCLR with a product asynchronous preset (AP) can be a product term oralways Select and EnableThe ATF1500A macrocell output can be selected as regis-tered or combinatorial.

9 When the output is registered, thesame registered signal is fed back internally to the globalbus. When the output is combinatorial, the buried feedbackcan be either the same combinatorial signal or it can be theregister output if the separate product term is chosen asthe flip -flop output enable multiplexer (MOE) controls the outputenable signals. Any buffer can be permanently enabled forsimple output operation. Buffers can also be permanentlydisabled to allow use of the pin as an input. In this configu-ration all the macrocell resources are still available, includ-ing the buried feedback, expander and CASCADE output enable for each macrocell can also be selectedas either of the two OE pins or as an individual BussesThe global bus contains all Input and I/O pin signals as wellas the buried feedback signal from all 32 with the complement of each signal, this providesa 68-bit bus as input to every product term.

10 Having theentire global bus available to each macrocell eliminatesany potential routing problems. With this architecturedesigns can be modified without requiring pinout macrocell also generates a foldback product signal goes to the regional bus, and is available to 16macrocells. The foldback is an inverse polarity of one of themacrocell s product terms. The 16 foldback terms in eachregion allow generation of high fan-in sum terms (up to 21product terms) with little additional (L)6 Note:1. All ICC parameters measured with outputs open, and a 16-bit loadable, up/down counter programmed into each Maximum Ratings*Temperature Under -40 C to +85 C*NOTICE:Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.