High- performance EPLD - Microchip Technology

1 1 TQFPTop View12345678910113332313029282726252423I /OI/OI/OGNDI/OI/OI/OI/OVCCI/OI/OI/OI/OI/ OI/OVCCI/OI/OI/OI/OGNDI/O444342414039383 73635341213141516171819202122I/OI/OI/OI/ OGNDVCCI/OI/OI/OI/OI/OI/OI/OI/O/PDVCCOE2 /IGCLR/IOE1/ICLK/IGNDI/OI/OPLCCTop View789101112131415161739383736353433323 13029I/OI/OI/OGNDI/OI/OI/OI/OVCCI/OI/OI/ OI/OI/OI/OVCCI/OI/OI/OI/OGNDI/O654321444 34241401819202122232425262728I/OI/OI/OI/ OGNDVCCI/OI/OI/OI/OI/OI/OI/OI/O/PDVCCOE2 /IGCLR/IOE1/ICLK/IGNDI/OI/OPin ConfigurationsPinNameFunctionCLKC lockILogic InputsI/OBi-directional BuffersGCLRR egister Reset (active low)OE1, OE2 Output Enable (active low)VCC+5V SupplyPDPower-down (active high )

2 Features High- density, High- performance Electrically-erasable Complex Programmable Logic Device 44-pin, 32 I/O CPLD ns Maximum Pin-to-pin Delay Registered Operation Up to 125 MHz Fully Connected Input and Feedback Logic Array Backward Compatibility with ATF1500/L Software and Hardware Flexible Logic Macrocell D/T/Latch Configurable Flip-flops Global and Individual Register Control Signals Global and Individual Output Enable Programmable Output Slew Rate Advanced Power Management Features Automatic 3 mA Standby (ATF1500AL)

3 Pin-controlled 10 mA Standby Mode Programmable Pin-keeper Inputs and I/Os Available in Commercial and Industrial Temperature Ranges Available in 44-lead PLCC and TQFP Packages Advanced Flash Technology 100% Tested Completely Reprogrammable 100 Program/Erase Cycles 20 Year Data Retention 2000V ESD Protection 200 mA Latch-up Immunity Supported by Popular third-arty Tools Security Fuse Feature Pin-compatible with the Most Commonly Used Devices Green (Pb/Halide-fee/RoHS Compliant) Package Options DescriptionThe ATF1500A is a High- performance , High- density complex PLD.

4 Built on anadvanced Flash Technology , it has maximum pin-to-pin delays of ns and supportssequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and upto 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic ATF1500A s global input and feedback architecture simplifies logic placementand eliminates pinout changes due to design performance EPLDATF1500 AATF1500 ALRev. 0759F 6/05(continued)ATF1500A(L)2 Functional Logic Diagram(1) connecting macrocells indicate direction and groupings of CASIN/CASOUT data ATF1500A has 32 bi-directional I/O pins and four dedi-cated input pins.

5 Each dedicated input pin can also serveas a global control signal: register clock, register reset oroutput enable. Each of these control signals can beselected for use individually within each of the 32 logic macrocells generates a buried feed-back, which goes to the global bus. Each input and I/O pinalso feeds into the global bus. Because of this global bus-ing, each of these signals is always available to all 32 mac-rocells in the (L)3 Each macrocell also generates a foldback logic term, whichgoes to a regional bus.

6 All signals within a regional bus areconnected to all 16 macrocells within the logic between macrocells in the ATF1500A allowsfast, efficient generation of complex logic functions. TheATF1500A contains four such logic chains, each capable ofcreating sum term logic with a fan-in of up to 40 productterms. Bus-friendly Pin-keeper Input and I/O sAll Input and I/O pins on the ATF1500A have programma-ble pin-keeper circuits. If activated, when any pin is drivenhigh or low and then subsequently left floating, it will stay atthat previous high or low level.

7 This circuitry prevents unused Input and I/O lines fromfloating to intermediate voltage levels, which causesunnecessary power consumption and system noise. Thekeeper circuits eliminate the need for external pull-up resis-tors and eliminate their DC power consumption. Pin-keeper circuits can be disabled. Programming is con-trolled in the logic design file. Once the pin-keeper circuitsare disabled, normal termination procedures are requiredfor unused inputs and ManagementThe ATF1500A has several built-in speed and power man-agement features.

8 The ATF1500A contains circuitry thatautomatically puts the device into a low-power standbymode when no logic transitions are occurring. This not onlyreduces power consumption during inactive periods, butalso provides proportional power savings for most applica-tions running at system speeds below 10 ATF1500As also have an optional pin-controlled power-down mode. In this mode, current drops to below 10 the power-down option is selected, the PD pin isused to power-down the part. The power-down option isselected in the design source file.

9 When enabled, thedevice goes into power-down when the PD pin is high . Inthe power-down mode, all internal logic signals are latchedand held, as are any enabled outputs. All pin transitions areignored until the PD is brought low. When the power-downfeature is enabled, the PD cannot be used as a logic inputor output. However, the PD pin s macrocell may stillbe used to generate buried foldback and cascadelogic output also has individual slew rate control. This maybe used to reduce system noise by slowing down outputsthat do not need to operate at maximum speed.

10 Outputsdefault to slow switching, and may be specified as fastswitching in the design file. Design Software SupportATF1500A designs are supported by several third-partytools. Automated fitters allow logic synthesis using a varietyof High- level description languages and DiagramI/O Diagram100 KVCCESDPROTECTIONCIRCUITINPUTPROGRAMMABL EOPTION100 KVCCVCCDATAOEI/OPROGRAMMABLEOPTIONATF150 0A(L)4 ATF1500A(L) MacrocellATF1500A MacrocellThe ATF1500A macrocell is flexible enough to supporthighly-complex logic functions operating at high speed.