i.MX RT1050 Crossover Processors Data Sheet for Consumer ...

1 NXP Semiconductors Document Number: IMXRT1050 CEC. Rev. 2, 03/2021. data Sheet : Technical data MIMXRT1051 DVL6A MIMXRT1052 DVL6A. MIMXRT1051 DVL6B MIMXRT1052 DVL6B. MIMXRT1051 DVJ6B MIMXRT1052 DVJ6B. MIMXRT105 SDVL6B. RT1050 Crossover Processors data Sheet for Consumer Products Package Information Plastic Package 196-pin MAPBGA, 10 x 10 mm, mm pitch 196-pin MAPBGA, 12 x 12 mm, mm pitch Ordering Information See Table 1 on page 5. 1 RT1050 introduction The RT1050 is a new processor family featuring 1. RT1050 introduction .. 1. NXP's advanced implementation of the Arm Features .. 2. Ordering information .. 5. Cortex -M7 core, which operates at speeds up to 600 2. Architectural overview .. 9. MHz to provide high CPU performance and best Block diagram .. 9. 3. Modules list .. 10. real-time response. Special signal considerations .. 16. Recommended connections for unused analog The RT1050 processor has 512 KB on-chip RAM, interfaces.

2 17. which can be flexibly configured as TCM or 4. Electrical characteristics .. 19. Chip-level conditions .. 19. general-purpose on-chip RAM. The RT1050 System power and clocks .. 26. integrates advanced power management module with I/O parameters .. 31. DCDC and LDO that reduces complexity of external System modules .. 38. External memory interface .. 43. power supply and simplifies power sequencing. The Display and graphics .. 53. RT1050 also provides various memory interfaces, Audio .. 56. Analog .. 59. including SDRAM, RAW NAND FLASH, NOR Communication interfaces .. 66. FLASH, SD/eMMC, Quad SPI, and a wide range of Timers .. 79. other interfaces for connecting peripherals, such as 5. Boot mode configuration .. 81. Boot mode configuration pins .. 81. WLAN, Bluetooth , GPS, displays, and camera Boot device interface allocation .. 81. sensors. The RT1050 also has rich audio and video 6. Package information and contact assignments.

3 86. 10 x 10 mm package information .. 86. features, including LCD display, basic 2D graphics, 12 x 12 mm package information .. 98. camera interface, SPDIF, and I2S audio interface. The 7. Revision history .. 110. NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. RT1050 introduction RT1050 has analog interfaces, such as ADC, ACMP, and TSC. The RT1050 is specifically useful for applications such as: Industrial Human Machine Interfaces (HMI). Motor Control Home Appliance Features The RT1050 Processors are based on Arm Cortex-M7 Core Platform, which has the following features: Supports single Arm Cortex-M7 Core with: 32 KB L1 Instruction Cache 32 KB L1 data Cache Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture Support the Armv7-M Thumb instruction set Integrated MPU, up to 16 individual protection regions Up to 512 KB I-TCM and D-TCM in total Frequency of 600 MHz Cortex M7 CoreSight components integration for debug Frequency of the core, as per Table 10, "Operating ranges," on page 21.

4 The SoC-level memory system consists of the following additional components: Boot ROM (96 KB). On-chip RAM (512 KB). Configurable RAM size up to 512 KB shared with M7 TCM. External memory interfaces: 8/16-bit SDRAM, up to SDRAM-166. 8/16-bit SLC NAND FLASH, with ECC handled in software SD/eMMC. SPI NOR/NAND FLASH. Parallel NOR FLASH with XIP support Single/Dual channel Quad SPI FLASH with XIP support Timers and PWMs: Two General Programmable Timers (GPT). 4-channel generic 32-bit resolution timer Each support standard capture and compare operation Four Periodical Interrupt Timer (PIT). Generic 16-bit resolution timer Periodical interrupt generation RT1050 Crossover Processors data Sheet for Consumer Products, Rev. 2, 03/2021. 2 NXP Semiconductors RT1050 introduction Four Quad Timers (QTimer). 4-channel generic 16-bit resolution timer for each Each support standard capture and compare operation Quadrature decoder integrated Four FlexPWMs Up to 8 individual PWM channels for each 16-bit resolution PWM suitable for Motor Control applications Four Quadrature Encoder/Decoders Each RT1050 processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously): Display Interface: Parallel RGB LCD interface Support 8/16/24 bit interface Support up to 1366 x 768 WXGA resolution Support Index color with 256 entry x 24 bit color LUT.

5 Smart LCD display with 8/16-bit MPU/8080 interface Audio: S/PDIF input and output Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and codec/DSP interfaces MQS interface for medium quality audio via GPIO pads Generic 2D graphics engine: BitBlit Flexible image composition options alpha, chroma key Image rotation (90 , 180 , 270 ). Porter-Daff operation Image size Color space conversion Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400). Standard 2D-DMA operation Camera sensors: Support 24-bit, 16-bit, and 8-bit CSI input Connectivity: Two USB OTG controllers with integrated PHY interfaces Two Ultra Secure Digital Host Controller (uSDHC) interfaces MMC compliance with HS200 support up to 200 MB/sec SD/SDIO compliance with 200 MHz SDR signaling to support up to 100 MB/sec RT1050 Crossover Processors data Sheet for Consumer Products, Rev. 2, 03/2021. NXP Semiconductors 3.

6 RT1050 introduction Support for SDXC (extended capacity). One 10/100 M Ethernet controller with support for IEEE1588. Eight universal asynchronous receiver/transmitter (UARTs) modules Four I2C modules Four SPI modules Two FlexCAN modules GPIO and Pin Multiplexing: General-purpose input/output (GPIO) modules with interrupt capability Input/output multiplexing controller (IOMUXC) to provide centralized pad control Two FlexIOs The RT1050 Processors integrate advanced power management unit and controllers: Full PMIC integration. On-chip DCDC and LDO. Temperature sensor with programmable trip points GPC hardware power management controller The RT1050 Processors support the following system debug: Arm CoreSight debug and trace architecture Trace Port Interface Unit (TPIU) to support off-chip real-time trace Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse Security functions are enabled and accelerated by the following hardware: High Assurance Boot (HAB).

7 data Co-Processor (DCP): AES-128, ECB, and CBC mode SHA-1 and SHA-256. CRC-32. Bus Encryption Engine (BEE). AES-128, ECB, and CTR mode On-the-fly QSPI Flash decryption True random number generation (TRNG). Secure Non-Volatile Storage (SNVS). Secure real-time clock (RTC). Zero Master Key (ZMK). Secure JTAG Controller (SJC). NOTE. The actual feature set depends on the part numbers as described in Table 1. Functions such as display and camera interfaces, connectivity interfaces, and security features are not offered on all derivatives. RT1050 Crossover Processors data Sheet for Consumer Products, Rev. 2, 03/2021. 4 NXP Semiconductors RT1050 introduction Ordering information Table 1 provides examples of orderable part numbers covered by this data Sheet . Table 1. Ordering information Junction Part Number Features Package Temperature Tj ( C). MIMXRT1051 DVJ6B 600 MHz, commercial eMMC x2 12 x 12 mm, mm pitch, 0 to +95.

8 grade for general SPI x4 196-pin MAPBGA. purpose with Ethernet MPU/FPU UART x8. eDMA I2C x4. Boot ROM (96 KB) FlexSPI. On-chip RAM (512 CAN x2. KB) FlexIO x2. SEMC 127 GPIOs GPT x2 HAB/DCP/BEE. 4-channel PIT TRNG. PWM x4 SNVS. ENC x4 SJC. WDOG x4 ADC x2. No LCD/CSI/PXP ACMP x4. SPDIF x1 TSC. SAI x3 DCDC. MQS x1 Temperature sensor USB OTG x2 GPC hardware power management controller MIMXRT1051 DVL6A 600 MHz, commercial eMMC x2 10 x 10 mm, mm pitch, 0 to +95. MIMXRT1051 DVL6B grade for general SPI x4 196-pin MAPBGA. purpose with Ethernet MPU/FPU UART x8. eDMA I2C x4. Boot ROM (96 KB) FlexSPI. On-chip RAM (512 CAN x2. KB) FlexIO x2. SEMC 127 GPIOs GPT x2 HAB/DCP/BEE. 4-channel PIT TRNG. PWM x4 SNVS. ENC x4 SJC. WDOG x4 ADC x2. No LCD/CSI/PXP ACMP x4. SPDIF x1 TSC. SAI x3 DCDC. MQS x1 Temperature sensor USB OTG x2 GPC hardware power management controller RT1050 Crossover Processors data Sheet for Consumer Products, Rev.

9 2, 03/2021. NXP Semiconductors 5. RT1050 introduction Table 1. Ordering information Junction Part Number Features Package Temperature Tj ( C). MIMXRT1052 DVJ6B 600 MHz, commercial eMMC x2 12 x 12 mm, mm pitch, 0 to +95. grade for general SPI x4 196-pin MAPBGA. purpose with Ethernet MPU/FPU UART x8. eDMA I2C x4. Boot ROM (96 KB) FlexSPI. On-chip RAM (512 CAN x2. KB) FlexIO x2. SEMC 127 GPIOs GPT x2 HAB/DCP/BEE. 4-channel PIT TRNG. PWM x4 SNVS. ENC x4 SJC. WDOG x4 ADC x2. LCD/CSI/PXP ACMP x4. SPDIF x1 TSC. SAI x3 DCDC. MQS x1 Temperature sensor USB OTG x2 GPC hardware power management controller RT1050 Crossover Processors data Sheet for Consumer Products, Rev. 2, 03/2021. 6 NXP Semiconductors RT1050 introduction Table 1. Ordering information Junction Part Number Features Package Temperature Tj ( C). MIMXRT1052 DVL6A 600 MHz, commercial eMMC x2 10 x 10 mm, mm pitch, 0 to +95. MIMXRT1052 DVL6B grade for general SPI x4 196-pin MAPBGA.

10 Purpose with Ethernet MPU/FPU UART x8. eDMA I2C x4. Boot ROM (96 KB) FlexSPI. On-chip RAM (512 CAN x2. KB) FlexIO x2. SEMC 127 GPIOs GPT x2 HAB/DCP/BEE. 4-channel PIT TRNG. PWM x4 SNVS. ENC x4 SJC. WDOG x4 ADC x2. LCD/CSI/PXP ACMP x4. SPDIF x1 TSC. SAI x3 DCDC. MQS x1 Temperature sensor USB OTG x2 GPC hardware power management controller MIMXRT105 SDVL6B 600 MHz, commercial 10 x 10 mm, mm pitch, 0 to +95. grade with MPU/FPU USB OTG x2 196-pin MAPBGA. Turnkey solution for eMMC x2. local voice (phoneme SPI x4. based) recognition, Ethernet see UART x8. I2C x4. cal2 FlexSPI. eDMA CAN x2. Boot ROM (92 KB) FlexIO x2. On-chip RAM (512 127 GPIOs KB) HAB/DCP/BEE. SEMC TRNG. GPT x2 SNVS. 4-channel PIT SJC. PWM x4 ADC x2. ENC x4 ACMP x4. WDOG x4 TSC. LCD/CSI/PXP DCDC. SPDIF x1 Temperature sensor SAI x3 GPC hardware power MQS x1 management controller Figure 1 describes the part number nomenclature so that characteristics of a specific part number can be identified (for example, cores, frequency, temperature grade , fuse options, and silicon revision).