ICM7555 General purpose CMOS timer - NXP

1 1. General descriptionThe ICM7555 is a cmos timer providing significantly improved performance over thestandard NE/SE555 timer , while at the same time being a direct replacement for thosedevices in most applications. Improved parameters include low supply current, wideoperating supply voltage range, low THRESHOLD,TRIGGER, andRESET currents, nocrowbarring of the supply current during output transitions, higher frequency performanceand no requirement to decouple CONTROL_VOLTAGE for stable ICM7555 is a stable controller capable of producing accurate time delays the one-shot mode, the pulse width of each circuit is precisely controlled by oneexternal resistor and capacitor. For astable operation as an oscillator, the free-runningfrequency and the duty cycle are both accurately controlled by two external resistors andone capacitor. Unlike the NE/SE555 device, the CONTROL_VOLTAGE terminal need notbe decoupled with a capacitor.

2 TheTRIGGER andRESET inputs are active LOW. Theoutput inverter can source or sink currents large enough to drive TTL loads or provideminimal offsets to drive cmos FeaturesnExact equivalent in most applications for NE/SE555nLow supply current: 80 A (typical)nExtremely low trigger, threshold, and reset currents: 20 pA (typical)nHigh-speed operation: 500 kHz guaranteednWide operating supply voltage range guaranteed 3 V to 16 V over full automotivetemperaturesnNormal reset function; no crowbarring of supply during output transitionnCan be used with higher-impedance timing elements than the NE/SE555 for longertime constantsnTiming from microseconds through hoursnOperates in both astable and monostable modesnAdjustable duty cyclenHigh output source/sink driver can drive TTL/CMOSnTypical temperature stability of % / C at 25 CnRail-to- rail outputsICM7555 General purpose cmos timerRev.

3 02 3 August 2009 Product data sheetICM7555_2 NXP 2009. All rights data sheetRev. 02 3 August 20092 of 22 NXP SemiconductorsICM7555 General purpose cmos timer3. ApplicationsnPrecision timingnPulse generationnSequential timingnTime delay generationnPulse width modulationnPulse position modulationnMissing pulse detector4. Ordering information5. Functional diagramTable informationType numberTemperature rangePackageNameDescriptionVersionICM755 5 CDTamb=0 C to +70 CSO8plastic small outline package; 8 leads; body width mmSOT96-1 ICM7555 IDTamb= 40 Cto+85 CICM7555 CNTamb=0 C to +70 CDIP8plastic dual in-line package; 8 leads (300 mil)SOT97-1 ICM7555 INTamb= 40 Cto+85 CRemark:Unused inputs should be connected to appropriate voltage diagram002aae403flip-flopRESET4comparato r AoutputdriversOUTPUT3 NDISCHARGEGND71comparator BRRRGND12 TRIGGERCONTROL_VOLTAGE5 THRESHOLD6 VDD8 ICM7555_2 NXP 2009.

4 All rights data sheetRev. 02 3 August 20093 of 22 NXP SemiconductorsICM7555 General purpose cmos timer6. Pinning Pin description7. Functional descriptionRefer toFigure 1 Functional diagram . Function selection[1]RESET will dominate all other inputs;TRIGGER will dominate over configuration for SO8 Fig configuration for DIP8 VDDDISCHARGETHRESHOLDCONTROL_VOLTAGEGNDT RIGGEROUTPUTRESETICM7555 CDICM7555ID002aae40012346587 ICM7555 CNICM7555 INGNDVDDTRIGGERDISCHARGEOUTPUTTHRESHOLDR ESETCONTROL_VOLTAGE002aae40112346587 Table descriptionSymbolPinDescriptionGND1suppl y groundTRIGGER2start timer input; (active LOW)OUTPUT3timer logic level outputRESET4timer inhibit input; (active LOW)CONTROL_VOLTAGE5timing capacitor upper voltage sense inputTHRESHOLD6timing capacitor lower voltage sense inputDISCHARGE7timing capacitor discharge outputVDD8supply voltageTable selectionTHRESHOLD voltageTRIGGER voltageRESET[1]OUTPUTD ischarge switchdon t caredon t careLLon>2 3V+>1 3V+HLonVth<2 3V+Vtrig>1 3V+Hstablestabledon t care<1 3V+HHoffICM7555_2 NXP 2009.

5 All rights data sheetRev. 02 3 August 20094 of 22 NXP SemiconductorsICM7555 General purpose cmos timer8. Limiting values[1]Due to the SCR structure inherent in the cmos process used to fabricate these devices, connecting any terminal to a voltage greaterthan VDD+ V or less than GND V may cause destructive latch-up. For this reason it is recommended that no inputs fromexternal sources not operating from the same power supply be applied to the device before its power supply is established. In multiplesystems, the supply of the ICM7555 must be turned on first.[2]Above 25 C, derate at the following rates:DIP8 package at mW / CSO8 package at mW / C[3]Refer toSection Power supply considerations CharacteristicsTable valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).SymbolParameterConditionsMinMaxUn itVDDsupply voltage18 VVIinput voltageTRIGGER[1] + + + + current-100mAPpower dissipationTamb=25 C (still air)[2][3]DIP8 package-1160mWSO8 package-780mWTstgstorage temperature 65+150 CTspsolder point temperaturesoldering 60 s-300 CTable C unless otherwise voltageTmin Tamb Tmax3-16 VIDD supply current[1]VDD=Vmin-50200 AVDD=Vmax-180300 AAstable mode timing[2][3] f/ffrequency f/ V frequency variation with f/ T frequency variation withtemperature[4]VDD= 5 V-50-ppm/ CVDD= 10 V-75-ppm/ CVDD= 15 V-100-ppm/ CVIinput voltageTRIGGER: VDD= 5 : VDD= 5 : VDD= 5 : VDD=Vminand NXP 2009.

6 All rights data sheetRev. 02 3 August 20095 of 22 NXP SemiconductorsICM7555 General purpose cmos timer [1]The supply current value is essentially independent of theTRIGGER, THRESHOLD andRESET voltages.[2]Astable timing is calculated using the following equation:The components are defined inFigure15.[3]RA, RB = 1 k to 100 k ; C = F; 5 V < VDD<15V[4]Parameter is not 100 % currentTRIGGERVDD=Vtrig=Vmax-50-pAVDD=Vt rig= 5 V-10-pAVDD=Vtrig=Vmin-1-pATHRESHOLDVDD=V th=Vmax-50-pAVDD=Vth=5V-10-pAVDD=Vth=Vmi n-1-pARESETVDD=Vrst=Vmax-100-pAVDD=Vrst= 5V-20-pAVDD=Vrst=Vmin-2-pAVOLLOW-level output voltageVDD=Vmax; Isink= ; Isink= output voltageIsource= mAVDD= voltageDISCHARGE:VDD=5V;IDIS= (o) output rise time[4]RL=10M ; CL= 10 pF;VDD=5V-4575nstf(o) output fall time[4]-2075nsfoscoscillator frequencyastable mode--500kHzTable ..continuedTamb=25 C unless otherwise +()C---------------------------------=IC M7555_2 NXP 2009.

7 All rights data sheetRev. 02 3 August 20096 of 22 NXP SemiconductorsICM7555 General purpose cmos timer10. Typical performance curvesFig current versus supply voltageTamb = +25 output voltage drop versus output source currentTamb = +25 low output voltage versus discharge sink currentVDD (V)02015105002aae40410015050200250 IDD( A)0 Tamb = 55 C+25 C+125 C002aae405 VDD VO (V)10 1102101101102Io(source)(mA)10 1 VDD = 18 V5 V2 V002aae406 VDIS (V)10 1101101102 IDIS(mA)10 1 VDD = 18 V5 V2 VICM7555_2 NXP 2009. All rights data sheetRev. 02 3 August 20097 of 22 NXP SemiconductorsICM7555 General purpose cmos timera. Tamb = +125 Tamb = +25 Tamb = 55 output voltage versus output sink current002aae407 VOL (V)10 1101101102Io(sink)(mA)10 1 VDD = 18 V5 V2 V002aae408 VOL (V)10 1101101102Io(sink)(mA)10 1 VDD = 18 V5 V2 V002aae409 VOL (V)10 1101101102Io(sink)(mA)10 1 VDD = 18 V5 V2 VICM7555_2 NXP 2009.

8 All rights data sheetRev. 02 3 August 20098 of 22 NXP SemiconductorsICM7555 General purpose cmos timerFig pulse width for triggeringFig delay versus voltage level ofTRIGGER pulse (VDD = 5 V)lowest voltage level of TRIGGER pulse (% VDD)040302010002aae4102003001004005000 TRIGGER pulse width (ns)VDD = 18 V5 V2 Vlowest voltage level of TRIGGER pulse (% VDD)040302010002aae41107505002501000tPD( ns)Tamb = 55 C+25 C+125 CICM7555_2 NXP 2009. All rights data sheetRev. 02 3 August 20099 of 22 NXP SemiconductorsICM7555 General purpose cmos timerTamb= +25 CRA=RB=10k C = FFig 10. Normalized frequency stability as a function of supply voltage (astable mode)RA=RB=1k C = FFig 11. Normalized frequency stability as a function of temperature (astable mode)VDD (V)02015105002aae41302 246 4normalized frequency(%)Tamb ( C) 751257525 25002aae414 420 24normalized frequency(%)VDD = 18 V5 V2 VICM7555_2 NXP 2009.

9 All rights data sheetRev. 02 3 August 200910 of 22 NXP SemiconductorsICM7555 General purpose cmos timerVDD=5V; Tamb= +25 CFig 12. Free-running frequency as a function of RA, RB resistance and externalcapacitanceVDD=5V; Tamb= +25 CFig 13. Monostable time delay versus RA resistance and external capacitance002aae415102C ( F)10 5f (Hz)10 110710 410610510410310210110 310 210 11101 k 10 k 100 k 1 M 10 M 002aae416102C ( F)10 5td (s)10 71010 4110 110 210 310 410 510 610 310 210 11101 k 10 k 100 k 1 M 10 M ICM7555_2 NXP 2009. All rights data sheetRev. 02 3 August 200911 of 22 NXP SemiconductorsICM7555 General purpose cmos timer11. Application GeneralThe ICM7555 device is, in most instances, a direct replacement for the NE/SE555 , it is possible to effect economies in the external component count using theICM7555. Because the NE/SE555 device produces large crowbar currents in the outputdriver, it is necessary to decouple the power supply lines with a good capacitor close tothe device.

10 The ICM7555 device produces no such transients. ICM7555 produces supply current spikes of only 2 mA to 3 mA instead of300 mA to 400 mA and supply decoupling is normally not necessary. Secondly, in mostinstances, the CONTROL_VOLTAGE decoupling capacitors are not required since theinput impedance of the cmos comparators on chip are very high. Thus, for manyapplications, 2 capacitors can be saved using an Power supply considerationsAlthough the supply current consumed by the ICM7555 device is very low, the totalsystem supply can be high unless the timing components are high-impedance. Therefore,high values for R and low values for C inFigure15 andFigure16 are output drive capabilityThe output driver consists of a cmos inverter capable of driving most logic familiesincluding cmos and TTL. As such, if driving cmos , the output swing at all supplyvoltages will equal the supply voltage.