Intel Stratix 10

1 PRODUCT LINEGX 400SX 400GX 650SX 650GX 850SX 850GX 1100SX 1100GX 1650SX 1650GX 2100SX 2100GX 2500SX 2500GX 2800SX 2800GX 1660GX 2110GX 10 MResourcesLogic elements (LEs)1378,000612,000841,0001,325,0001,62 4,0002,005,0002,422,0002,753,0001,679,00 02,073,000 10,200,000 Adaptive logic modules (ALMs)128,160207,360284,960449,280550,54 0679,680821,150933,120569,200702,720 3,466,080 ALM registers512,640829,4401,139,8401,797,12 02,202,1602,718,7203,284,6003,732,4802,2 76,8002,810,880 13,864,320 Hyper-Registers from Intel HyperflexTM FPGA architectureMillions of Hyper-Registers distributed throughout the monolithic FPGA fabricProgrammable clock trees synthesizableHundreds of synthesizable clock treesM20K memory blocks1,5372,4893,4775,4615,8516,5019,96 311,7216,1626,847 12,950 M20K memory size (Mb)304968107114127195229120134 253 MLAB memory size (Mb)

2 23478111315911 55 Variable-precision digital signal processing (DSP) blocks6481,1522,0162,5923,1453,7445,0115 ,7603,3263,960 3,456 18 x 19 multipliers1,2962,3044,0325,1846,2907,48 810,02211,5206,6527,920 6,912 Peak fixed-point performance (TMACS) Peak floating-point performance (TFLOPS) I/O and Architectural FeaturesSecure device managerAES-256/SHA-256 bitsream encryption/authentication, physically unclonable function (PUF), ECDSA 256/384 boot code authentication, side channel attack protection Hard processor system4 Quad-core 64-bit ARM* Cortex*-A53 up to GHz with 32KB I/D cache, NEON coprocessor, 1 MB L2 Cache, direct memory access (DMA), system memory management unit, cache coherency unit, hard memory controllers, USB x2, 1G EMAC x3, UART x2, SPI x4, I2C x5, general purpose timers x7, watchdog timer x4 SX 400SX 650SX 850SX 1100SX 1650SX 2100SX 2500SX 2800 Maximum user I/O pins37439268868870470411601160688688 2,304 Maximum LVDS pairs Gbps (RX or TX)

3 192192336336336336576576336336 11525 Total full duplex transceiver count24244848969696964848 48 GXT full duplex transceiver count (up to Gbps)16163232646464643232 GX full duplex transceiver count (up to Gbps)881616323232321616 48 PCI Express* (PCIe*) hard intellectual property (IP) blocks (Gen3 x16)1122444422 46 Memory devices supportedDDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSysPackage Options and I/O Pins: General-Purpose I/O (GPIO) Count, High-Voltage I/O Count, LVDS Pairs, and Transceiver Count7, 8F1152 pin (35 mm x 35 mm, mm pitch)392,8,192,24392,8,192,24 F1760 pin ( mm x mm, mm pitch) 688,16,336,48688,16,336,48688,16,336,486 88,16,336,48688,16,336,48688,16,336,4868 8,16,336,48688,16,336,48F2397 pin (50 mm x 50 mm, mm pitch) 704,32,336,96704,32,336,96704,32,336,967 04,32,336,96 F2912 pin (55 mm x 55 mm, mm pitch) 1160,8,576,241160,8,576,24 F4938 pin (70 mm x 74 mm, mm pitch)2304, 32, 1152, 48 Notes:1.

4 LE counts valid in comparing across Intel FPGA devices, and are conservative vs. competing Fixed point performance assumes the use of Floating point performance is IEEE-754 compliant Quad-core ARM Cortex-A53 hard processor system only available in Stratix 10 SX Gbps LVDS maximum rate for GX PCIe Gen3 x 8 support for GX A subset of pins for each package are used for high-voltage V and V All data is preliminary and subject to change without prior ,8,192,24 Numbers indicate total GPIO count, high-voltage I/O count, LVDS pairs, and transceiver pin migration Stratix 10 GX/SX Product Table Intel Corporation.

5 Intel , the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of LINESX 400SX 650SX 850SX 1100SX 1650SX 2100SX 2500SX 2800 ProcessorQuad-core 64 bit ARM Cortex-A53 MPCore* processorMaximum processor GHz1 Processor cache and co-processors L1 instruction cache (32 KB) L1 data cache (32 KB) with error correction code (ECC) Level 2 cache (1 MB) with ECC Floating-point unit (FPU) single and double precision ARM NEON media engine ARM CoreSight* debug and trace technology System Memory Management Unit (SMMU) Cache Coherency Unit (CCU)

6 Scratch pad RAM256 KBHPS DDR memoryDDR4, DDR3 (Up to 64 bit with ECC) Direct memory access (DMA) controller8 channelsEMAC3X 10/100/1000 Ethernet media access controller (EMAC) with integrated DMAUSB on-the-go (OTG) controller2X USB OTG with integrated DMAUART controller2X UART 16550 compatibleSerial peripheral interface (SPI) controller4X SPII2C controller5X I2 CQuad SPI flash controller1X SIO, DIO, QIO SPI flash supportedSD/SDIO/MMC controller1X eMMC with DMA and CE-ATA supportNAND flash controller 1X ONFI or later 8 and 16 bit supportGeneral-purpose timers4X Software-programmable general-purpose I/Os (GPIOs)Maximum 48 GPIOsHPS DDR Shared I/O3X 48 - May be assigned to HPS for HPS DDR accessDirect I/Os48 I/Os to connect HPS peripherals directly to I/OWatchdog timers4X SecuritySecure device manager, Advanced Encryption Standard (AES)

7 AES-256/SHA-256 bitsream encryption/authentication, PUF, ECDSA 256/384 boot code authentication, side channel attack protectionNotes:1. With overdrive e n -1023 -2. 0 Intel Stratix 10 GX/SX Product Tabl