Interfacing Between LVPECL, VML, CML and LVDS …

1 Application ReportSLLA120 - December 20021 Interfacing Between lvpecl , VML, CML, and LVDS LevelsNick HollandSerial Gigabit SolutionsABSTRACTThis application report introduces the various interface standards used today in moderntelecom and datacom systems and describes the methods used to interface Between similarand different I/O structures used on Texas Instruments serial gigabit solutions products. Themain logic levels discussed in this application report are low-voltage positive/pseudoemitter-coupled logic ( lvpecl ), current-mode logic (CML), voltage-mode logic (VML) andlow-voltage differential signaling (LVDS). This document focuses on these four logic levels,because they are now the most prevalent in today s communications systems. Thisdocument deals with the different SERDES devices from Texas Instruments, frominput/output structures, various high-speed drivers and receivers, receiver biasing, andtermination schemes.

2 Explanations and examples on how to interface different types ofdrivers and receivers using ac-coupling are also .. 2 Switching Levels3.. 3 Output and Input Stages4.. lvpecl Interface Structures5.. lvpecl Output Stage5.. Input Stage for Devices Using lvpecl Drivers6.. CML Interface Structures6.. CML Output Stage6.. Input Stage for Devices Requiring CML Signaling Levels7.. VML Interface Structures8.. VML Output Stage8.. Input Stage for Devices Requiring VML Signaling Levels9.. LVDS Interface Structures10.. LVDS Output Stage10.. Input Stage for Devices Requiring LVDS Signaling Levels11.. 4 Interfacing Texas Instruments SERDES Devices12.. LVPECL12.. lvpecl Driver DC-Coupled12.. lvpecl Driver AC-Coupled13.. CML13.. Current Mode Logic (CML) Driver DC-Coupled13.. Current Mode Logic (CML) Driver AC-Coupled14.. VML14.. Trademarks are the property of their respective Between lvpecl , VML, CML, and LVDS Voltage Mode Logic (VML) Drivers DC-Coupled14.

3 Voltage Mode Logic (VML) Drivers AC-Coupled15.. Low-Voltage Differential Signaling (LVDS) Drivers DC-COupled16.. 5 Biasing and Termination Schemes16.. Biasing16.. Termination Schemes17.. Differential Scheme17.. Differential Scheme With Decoupling Capacitor18.. Differential Scheme With Reduced Resistor Count19.. Differential Scheme With One Biasing Network21.. Internal Termination and Biasing Summary22.. List of Figures1 Graphic Voltage Swings by Logic Level4.. 2 Typical Structure for an lvpecl Output Stage5.. 3 Input Stage for Devices Requiring lvpecl Signaling Levels6.. 4 Typical Structure for a CML Output Stage7.. 5 Input Stage for Devices Requiring CML Signaling Levels8.. 6 Typical Structure for a VML Output Stage9.. 7 Input Stage for Devices Requiring VML Signaling Levels10.. 8 Typical Structure for an LVDS Output Stage11.. 9 Input Stage for Devices Requiring LVDS Signaling Levels12.. 10 lvpecl Driver for DC-Coupling13.

4 11 lvpecl Driver for AC-Coupling13.. 12 CML Driver for DC-Coupling14.. 13 CML Driver for AC-Coupling14.. 14 VML Driver for DC-Coupling15.. 15 Split Differential Termination With Capacitor15.. 16 VML Driver for AC-Coupling15.. 17 LVDS Driver for DC-Coupling16.. 18 Simple Resistor Network for Biasing Voltages16.. 19 Example With VML Driver and Receiver Requiring CML Voltage Levels17.. 20 Differential Termination With Biasing18.. 21 Differential Termination With Biasing and Decoupling Capacitor18.. 22 Differential Termination With Reduced Resistor Count19.. 23 Example With VML Driver and Receiver Requiring CML Voltage Levels20.. 24 Differential Termination With One Biasing Network21.. List of Tables1 Voltage Parameters by Logic Level3.. 2 Logic Level by TI Device4.. SLLA1203 Interfacing Between lvpecl , VML, CML, and LVDS Levels1 IntroductionAs the communications industry is moving to faster data speeds and from parallel- toserial-based technologies, the variety of Interfacing standards has led to concerns on how tointerface these different logic levels together.

5 The main three priorities for the industry have beento increase performance, decrease power consumption, and reduce cost. Earlier technologies,such as emitter-coupled logic (ECL), used an inconvenient negative power supply rail, which atthe time had the advantage of improved noise immunity. Since the implementation ofpositive-supply technologies such as TLL and CMOS, the older technologies no longer provide abenefit, as a system using them would require several power supplies including the V or V needed for a result, ECL migrated to positive/pseudo emitter-coupled logic (PECL), which alloweddesigners to move away from this negative supply rail and simplify board layout. The principlebehind PECL was simply to keep the same output swing of 800 mV, but shift it to a positivevoltage by using a 5-V rail and ground. Low-voltage positive/pseudo emitter coupled logic( lvpecl ) is the same concept as PECL, but uses a supply rather that the 5-V one. Thisresulted in a power consumption reduction relative to , as more and more designs use CMOS-based technology, new high-speed drivershave been introduced, such as current mode logic (CML), voltage mode logic (VML), andlow-voltage differential signaling (LVDS).

6 This has led to many combinations of switching levelswithin a system that need to interface with each application report focuses on the different SERDES devices from Texas Instruments,input/output structures, various high-speed drivers, and biasing and termination types of drivers and receivers can be interfaced, especially if ac-coupling is using ac-coupling, the drivers and receivers are treated separately. AC-coupling iscommonly used: To interface different technology types To interface different signal voltages , driver and receiver To interface different ground references Between driver and receiverNote that when ac-coupling is used, the driver and receiver can be treated LevelsThe first step in understanding how to interface the various drivers and receivers associated withthe logic levels discussed in the application report is to visualize the output voltage swings andbiasing voltages. The main voltage levels discussed in this application report are lvpecl , CML,VML, and 1 outlines the typical output levels and common-mode voltages for existing TexasInstruments SERDES 1.

7 Voltage Parameters by Logic V1 VOutput voltage (single ended)800 mV800 mV800 mV400 mVCommon-mode voltage2 VSLLA1204 Interfacing Between lvpecl , VML, CML, and LVDS LevelsAn even better method is a visual representation, as shown in Figure 1. The swings shownbelow are for = 2 VVOH = VVOH = V800 mVVMLVCM = VVOH = VVOH = V800 mVCMLVCM = VVOH = VVOH = V800 mVLVDSVCM = VVOH = VVOH = 1 V400 mVFigure 1. Graphic Voltage Swings by Logic LevelAnother vital point is to introduce which Texas Instruments serial gigabit solution SERDES devices have which kind of output drivers. This is listed in Table 2. Logic Level by TI DeviceTI PART NUMBERLVPECLCMLVMLLVDSTNETE2201BX TLK1501 X TLK2501 X TLK2701 X TLK2711 X TLK3101 X TLK1201 X TLK2201 X TLK2208 X TLK31x4 X TLK4015 X SLK25x1 X SLK27x1 X SLK2504 X SN65 LVDS9x XSN65LV1021/1212 XSN65LV1023/1224 XNow that the switching levels have been introduced along with which Texas Instruments partsinclude which type of drivers, the next step is to describe how the different input and outputstages are designed.

8 This allows the reader to understand how to interface the various logiclevels and Input StagesAs mentioned earlier, it is only relevant to talk about lvpecl , CML, VML and LVDS drivers,because these are the main types of drivers used in CMOS technologies. The section introduceseach type of output and input Interfacing Between lvpecl , VML, CML, and LVDS Interface StructuresLVPECL is derived from ECL and PECL and typically uses V and ground supply current Texas Instruments serial gigabit solution device that has an integrated lvpecl driver is the TNETE2201 Output StageThe typical output of an lvpecl driver consists of a differential pair with the emitters connectedto ground via a current source. This differential pair drives a pair of emitter-followers whichprovide the current to Output+ and Output . The lvpecl output stage requires a terminationresistance of 50 to the bias voltage of VCC 2 V. This implies that the emitters of the pair offollowers are around VCC V, because there is a drop across the base-emitterjunction.

9 The drop across the 50- termination resistors results in a 14-mA flow throughthe PECL driver. Because the output impedance of the driver is lower than 50 , care must betaken that correct termination is used to reduce voltage reflections that occur due to +Output GNDC urrent SourceVCC50 50 VCC*2 VFigure 2. Typical Structure for an lvpecl Output StageSLLA1206 Interfacing Between lvpecl , VML, CML, and LVDS Stage for Devices Using lvpecl DriversThe TNETE2201 input stage consists of a differential pair which requires its inputs (Input+ andInput ) to be pulled up via resistors to VCC V in order to provide a common-mode voltageof 2 V in the case where VCC is V. This is shown more clearly in the Interfacing section of thisreport. If input biasing is not included on-chip, this must be taken care of on the PCB, and theresistors should be placed as close to the device pins as +Input GNDC urrent SourceVCCF igure 3. Input Stage for Devices Requiring lvpecl Signaling Interface StructuresThe CML interface drivers provide several design features, including high-speed capabilities,adjustable logic output swing, level adjustment, and adjustable slew rate.

10 Current TexasInstruments serial gigabit solution devices that have an integrated CML driver are the TLK1501,TLK2501, TLK2701, and Output StageThe above devices have CML drivers that are built from an open-drain differential pair and avoltage-controlled current source using NMOS transistors. The outputs (Output+ and Output )require pullup resistors to VDD because the NMOS transistor can drive only falling edgesefficiently and needs the pullups to help drive rising edges. The voltage-controlled currentsource is used to vary the amount of current used to drive the load, because the output voltageswing is load dependent. The load resistors and the external reference resistor can then bechosen to optimize output voltage Interfacing Between lvpecl , VML, CML, and LVDS LevelsGNDANMOSNMOSNMOSO utput Voltage ControlledCurrent SourceOutput +Figure 4. Typical Structure for a CML Output Stage for Devices Requiring CML Signaling LevelsThe typical input stage for Texas Instruments devices designed for CML signaling consists of adifferential pair using NMOS transistors, and the inputs (Input+ and Input ) require pullupresistors to the common-mode voltage of the receiver.