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Introduction to PLLs - Engineering

Introduction to PLLs Behzad Razavi Electrical Engineering Department University of California, Los Angeles 1. Outline z Need for Frequency Synthesis z Phase Detector z Type I and II PLLs z PFD/Charge Pump Nonidealities z PLL Design Procedure 2. The Need for RF Synthesis z What happens if the LO z Need a freq. synthesizer: freq is not exactly what we want? 3. Mathematical Model of VCO. zWhat happens if a small sine appears on Vcont? 4. Phase Detector 5. Problem of Phase Alignment z Loop is locked if phase difference is constant. 6. Example z Ripple modulates VCO, producing sidebands. 7. Response to Frequency Step 8. Response to Phase Step 9. Phase and Frequency Settling 10. PLL Dynamics z How do we compute the time or frequency response of a PLL? 11. Type I PLL. z Trade-offs among stability, ripple, and phase offset z Limited capture range zWhy is this better than a piece of wire?

29 Charge Pump Design zSelect W/L of current sources for an overdrive of about 50-100 mV. zChoose L such that mismatch due to channel- length modulation remains below 10-20%. zChoose switch dimensions for a headroom consumption of 20-30 mV. zIf mismatch due to channel-length modulation results in excessive jitter or sidebands: (a) Increase C 2 and Cp (BW goes down).

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Transcription of Introduction to PLLs - Engineering

1 Introduction to PLLs Behzad Razavi Electrical Engineering Department University of California, Los Angeles 1. Outline z Need for Frequency Synthesis z Phase Detector z Type I and II PLLs z PFD/Charge Pump Nonidealities z PLL Design Procedure 2. The Need for RF Synthesis z What happens if the LO z Need a freq. synthesizer: freq is not exactly what we want? 3. Mathematical Model of VCO. zWhat happens if a small sine appears on Vcont? 4. Phase Detector 5. Problem of Phase Alignment z Loop is locked if phase difference is constant. 6. Example z Ripple modulates VCO, producing sidebands. 7. Response to Frequency Step 8. Response to Phase Step 9. Phase and Frequency Settling 10. PLL Dynamics z How do we compute the time or frequency response of a PLL? 11. Type I PLL. z Trade-offs among stability, ripple, and phase offset z Limited capture range zWhy is this better than a piece of wire?

2 12. Frequency Multiplication Voltage Type Phase or Freq Type z How do these change for this type of loop: 13. Aided Acquisition 14. PFD Implementation z Reset pulses are ~ 5 gate delays wide. z Reset pulses are necessary to avoid dead zone.. 15. PFD and Charge Pump z Infinite gain yields zero phase offset. z Q. A and QB are called Up and Down pulses, respectively. 16. PFD/CP/Capacitor Behavior 17. First Attempt to Close the Loop 18. Type II (Charge-Pump) PLL. 19. Frequency Multiplication Revisited 20. PFD/CP Nonidealities z Skew between Up and Down Pulses z Mismatch between Up and Down Currents z Charge Sharing z Channel-Length Modulation z Charge Injection Mismatch 21. Problem of Skew 22. Up and Down Current Mismatch z Produces both ripple and phase offset. 23. Channel-Length Modulation W/LN=10 um/60 nm Ix W/LN=20 um/120 nm Vx 24.

3 Reduction of Channel-Length Modulation [Lee, Elec. Let., Nov. 00] [Terrovitis, ISSCC04]. 25. Reduction of Both Mismatches [Wakayama, US Patent 7,057,465 B2]. (Also, see Gierkink, ISSCC08]. 26. Addition of Second Capacitor z C2 can reach with little degradation in settling behavior. z But imposes an upper bound on Rp. 27. PLL Design Procedure z Design VCO for frequency range of interest and obtain KVCO. z Set the loop bandwidth to one-tenth of input frequency: (Loop BW ~ n for = 1.). z Select a charge pump current (tens of microamps to some milliamps). z Set the damping factor to 1 and compute Rp and Cp. 28. Charge Pump Design z Select W/L of current sources for an overdrive of about 50-100 mV. z Choose L such that mismatch due to channel- length modulation remains below 10-20%. z Choose switch dimensions for a headroom consumption of 20-30 mV.)

4 Z If mismatch due to channel-length modulation results in excessive jitter or sidebands: (a) Increase C2 and Cp (BW goes down). (b) Use one of the circuit techniques to reduce effect of channel-length modulation. Ip= mA KVCO=148 MHz/V. 235 MHz 29. M=4. Simulated Behavior Rp= k Rp=3 k Rp=6 k Cp=25 p Cp=25 p Cp=25 p C2=5 p C2=5 p C2=5 p Rp=12 k Rp=3 k Rp= k Cp=25 p Cp=25 p Cp=25 p C2=5 p C2= p C2= p 30.


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