jfet basics - kennethkuhn.com

1 jfet Basics1by Kenneth A. KuhnNov. 3, 2001, rev. Oct. 30, 2008 IntroductionAjunctionfield- effect transistor ( jfet )consists of a semiconducting channel whoseconductance is controlled by an electric field . The terminals at either end of the channelare called source(S)and drain(D). The control electrode that applies the electric fieldiscalled the gate(G)and is made of the opposite type of semiconductor material than , there is a PN junction between the gate and the PNjunction is always reverse biased in normal 1 shows the basic 1: jfet construction and conduction channel controlled by depletion zoneJFETs are known as depletion mode devices because the channel conducts with zerobiasvoltage applied ( the depletion region has zero width).

2 Applying a reverse biasincreases the width of the depletion region which in turnreduces the conduction of is the basis for making an channel conduction resembles aresistor for low voltage drops(ohmic region)and becomes a constant current for highervoltage drops(saturation region).The mathematical models we use are based on thesaturation region and will provide incorrect results if used in the for a field effect transistor is a voltage controlled current JFETs areso symmetrical in their construction that it makes little if any difference if the source anddrain terminals are are two channel types of JFETs. One type is n-channel and the other type is p-channel. Both types operate exactly the same way but the terminal voltages and currentsare discussion isfor n-channel Basics2 The main feature of JFETs is extremely high inputresistance usuallyat least severalhundred megohms.

3 This feature enables the power gain of a jfet amplifier to be of analytic equations for jfet bias conditionThefollowing discussion is about n-channel JFETs. p-channel JFETs operate the sameway except that the polarity of the terminal voltages and currents is inverted. There aretwo parameters that describe the operation of a jfet :IDSSis the drain saturation current at VGS= the gate-source voltage, VGS, that causes the channel conduction to drop to zero(actually, the drain current does not go all the way to zero but ceases to decreasebelow a very small current).IDSSand VPhave a rough proportional relationship. A high IDSS generally has a highermagnitude , because the relationship is dependent on the manufacturinggeometry of the jfet there is not a singular proportionality constant.

4 The interpretationof this is that for the spread of IDSSand VPprovided on the data sheet for a specific partthat low values of one parameter tend to correlate with low values of the other parameterwith the same holding true for higher data sheets show atypicalplot of drain current is zero when VGS= VPand is IDSS when VGS=0. The relationship inthe saturation region follows a square law as shown in Equation normal operation,VGSis biased to be somewhere between VPand0. Equation 1gives the approximatedrain current, ID, for a given bias point. This approximation is generally good to withinabout ten percent and is the accepted equation for all jfet more exactmodel is discussed IDSS* [1-(VGS/VP)]2Eq. 1 Equation 1 is valid only if the jfet is operating such that VGSis between 0 and VPandthat VDSis greater than (VGS-VP), the saturation region.

5 Note that the drain current,ID, will be between 0 and 2illustrates an example transfer function for aJFET that has an IDSSof 12 mA and a VPof-6 volts. The drain current will be less if thetransistor is operating in the ohmic region. Although the transfer curve continues into thepositive bias region we do not normally operate the jfet there except for very Basics3 Transfer Curve of a Typical 2: Transfer Curve of a Typical jfet showing IDversus VGSF igure 3shows the family curves for a typical jfet . For amplifiers we normally operatethe jfet in the saturation region to the right of the dotted parabola curve that separatesthe ohmic region from the saturation region. Note that that the dotted curve is thesolution to VDS=(VGS VP).

6 In the ohmic region the device acts similarly to a voltagecontrolled resistor and in the saturation region the device acts as a voltage controlledcurrent source. The slight tilt of the lines in the saturation region is an extension of themodel that includes the effective shunt resistance of the current source. That model is notdiscussed here. All of the mathematics developed later assumes these lines are should be noted thatfor VDSnear zero volts(within plus or minus a fewtenths of a volt at most)the channel acts as a voltage variable resistorthat is linear withvoltage. This useful effect continues through zero for small negative voltages across Basics4 FET Family IDSS = 12 mA and VP = -6 Ohmic_regionSaturation_regionFigure 3: FET Family CurvesNote: VGSis negative the minus sign may not show on some systemsIt is desirable to have the solution to every possible permutation of knowns.

7 The nexttask is to solve Equation 1 for VGSif IDis known. This isan exercise for the student butthe result is:VGS= VP* [1-sqrt(ID/IDSS)]Eq. 2 Equations 1 and 2 tell us about the DC bias point operation of the jfet for anycombination of of gain equations for theJFETS ince the jfet is a voltage controlled current source, the gain is the change in draincurrent divided by the change in gate voltage. This is called thetransconductance gain(abbreviated asgm)of the JFETand has units ofconductance which is measured gain value is very low(typically between and but rememberthat what matters is power gain and that is very high for a jfet )and is often expressed inmS. The gain is found by taking thederivative of Equation 1with respect to |2 * (IDSS/VP) * [1-(VGS/VP)]|Eq.

8 3 jfet Basics5 The absolute value is used becausegmis alwayspositive. This is done because signinformation is lost when terms are squared as in Equation 1. The ratio, IDSS/VP, willalways be negativesince VPis negativefor n-channelJFETS and IDSSis negative for p-channel from Equation 3 that gmis a linear function of VGS. When VGSis equal to VP( IDis zero) then gmis zero. When VGSis equal to zero ( ID= IDSS) then gmis at themaximum value. The maximum value of gmis known as gmoand is obtained by settingVGSto zero in Equation |2 * (IDSS/VP)|Eq. 4At this point it should seem obvious that if high gain is desired then the jfet should bebiased asclose as practical to IDSS. Equation 4 gives us the ultimate gain 3 gives us the gmif VGSis known.

9 For some problems, IDis known VGScan be calculated if IDis known, it is convenient to have an equation thatdirectlygives us gmwhen IDis known. Simple substitution of Equation 1 into Equation 3(an exercise for the student) gives:gm= |2 * sqrt(ID* IDSS) / VP|Eq. 5 Equation 5 can be expressed in another way that mightbe convenient for some problemsgm= gmo* sqrt(ID/IDSS)Eq. 6 All three waysof computing gmgive exactly the same answer. The one to use depends onwhat the knowns at the moment must be remembered that all of these equationsassume the jfet is operating in the saturation region. They do not apply in the user must always take care in using these scale factor of 2 in Equations 3 through 5 is nominal. According to the NationalSemiconductor FET Handbook (1977), that factor can rangefrom about to but istypically near 2.

10 Keep in mind that we use a model of a jfet based on a simplifiedquadratic 1 and 2 can be expressed in a normalized formasID/IDSS= [1 (VGS/VP)]2Eq. 7 VGS/VP= 1 sqrt(ID/IDSS)Eq. 8 jfet Basics6An equation for the normalized gmcan be developed by dividing Equation 3 by Equation4 producinggm/gmo= 1 VGS/VPEq. 9By substituting Equation 8 into Equation 9 we can also writegm/gmo= sqrt(ID/IDSS)Eq. 10 Figure 4is a plotof Equations 7 and 9. The linear relationship between VGSand gmisclearly seen. Figure 5is a plot of Equation ID/IDSS and gm/gmo versus : Normalized FET plotJFET Basics7gm/gmo versus 5: Normalized gm/gmoComparing Exact and ApproximateJFETM odelsIn the text, Engineering Electronics, A Practical Approach, by Robert Mauro (copyright1989 by Prentice-Hall, Inc.)