MCP19118/19 Data Sheet - Microchip Technology

1 2014 Microchip Technology 1 Synchronous Buck Features: Input Voltage: to 40V Output Voltage: to Greater than requires external divider Switching Frequency: 100 kHz to MHz Quiescent Current: 5 mA Typical High-Drive:- +5V Gate Drive- 1A/2A Source Current- 1A/2A Sink Current Low-Drive:- +5V Gate Drive- 2A Source Current- 4A Sink Current Peak Current Mode Control Differential Remote Output Sense QEC-100 Qualified Multiple Output Systems:- Master or Slave- Frequency Synchronized Configurable Parameters:- Overcurrent Limit- Input Undervoltage Lockout- Output Overvoltage- Output Undervoltage- Internal Analog Compensation- Soft Start Profile- Synchronous Driver Dead Time- Switching Frequency Thermal ShutdownMicrocontroller Features: Precision 8 MHz Internal Oscillator Block:- Factory Calibrated Interrupt Capable-Firmware- Interrupt-on-Change Pins Only 35 Instructions to Learn 4096 Words On-Chip Program Memory High-Endurance Flash:- 100,000 Write Flash Endurance- Flash Retention: >40 years Watchdog Timer (WDT) with Independent Oscillator for Reliable Operation Programmable Code Protection In-Circuit Debug (ICD) via Two Pins (MCP19119) In-Circuit Serial Programming (ICSP ) via Two Pins 11 I/O Pins and One Input-Only Pin ( mcp19118 )- Three Open-Drain Pins 14 I/O Pins and One Input-Only Pin (MCP19119)- Three Open-Drain Pins Analog-to-Digital Converter (ADC):- 10-Bit Resolution- 12 Internal Channels- Eight External Channels Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler Enhanced Timer1:- 16-Bit Timer/Counter with Prescaler- Two Selectable Clock Sources Timer2.

2 8-Bit Timer/Counter with Prescaler- 8-Bit Period Register I2 CTM Communication:- 7-Bit Address Masking- Two Dedicated Address Registers- SMBus/PMBusTM CompatibilityMCP19118/19 Digitally-Enhanced Power Analog Controller with Integrated Synchronous DriverMCP19118/19DS20005350A-page 2 2014 Microchip Technology Diagram 24-Pin QFN ( mcp19118 ) mcp19118 GPA2 GPA4 GPB0 GPA1 GPA0 GPA3 GPA7 VINGPB2 GPA5/MCLRPGNDLDRVVDRPHASEHDRVBOOTVDDGPB1 -VSEN+VSEN+ISEN-ISENGPA6 GND1234561378910111214151617182322212019 24 EXP-25 2014 Microchip Technology 3 MCP19118/19 TABLE 1:24-PIN SUMMARYI/O24-Pin QFNANSELA/DTimersMSSPI nterruptPull-UpBasicAdditionalGPA01 YAN0 IOCY Analog Debug Output (1)GPA12 YAN1 IOCY Sync. Signal In/Out (2, 3)GPA23 YAN2T0 CKI IOCINTY GPA35 YAN3 IOCY GPA48N IOCN GPA57N IOC(4)Y(5)MCLR GPA66N IOCNICSPDAT GPA75N SCLIOCNICSPCLK GPB09N SDAIOCN GPB123 YAN4 IOCY Error Signal In/Out (3)GPB224 YAN5 IOCY VIN11N VIND evice Input VoltageVDR14N VDRGate Drive Supply Input VoltageVDD18N VDDI nternal Regulator Output GND10N GNDS mall Signal GroundPGND12N Large Signal GroundLDRV13N Low-Side MOSFETC onnectionHDRV16N High-Side MOSFETC onnectionPHASE15N Switch NodeBOOT17N Floating Bootstrap Supply+VSEN21N Output Voltage Differential Sense-VSEN22N Output Voltage Differential Sense+ISEN20N Current Sense Input-ISEN19N Current Sense InputNote 1:The Analog Debug Output is selected when the ATSTCON<BNCHEN> bit is.

3 Selected when the device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits in the BUFFCON :Selected when the device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in the BUFFCON :The IOC is disabled when MCLR is :Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. mcp19118 /19DS20005350A-page 4 2014 Microchip Technology Diagram 28-Pin QFN (MCP19119)MCP19119 GPA2 GPB4 GPA4 GPB7 GPB0 GPA1 GPA0 GPA3 GPA7 VINGPB2 GPA5/MCLRPGNDLDRVVDRPHASEHDRVBOOTVDDGPB1 -VSEN+VSEN+ISEN-ISENGPA6 GNDGPB6 GPB5123456715891011121314161718192021262 52423222827 EXP-29 2014 Microchip Technology 5 MCP19118/19 TABLE 2:28-PIN SUMMARYI/O28-Pin QFNANSELA/DTimersMSSPI nterruptPull-UpBasicAdditionalGPA01 YAN0 IOCY Analog Debug Output (1)GPA12 YAN1 IOCY Sync.

4 Signal In/Out (2, 3)GPA23 YAN2T0 CKI IOCINTY GPA35 YAN3 IOCY GPA49N IOCN GPA58N IOC(4)Y(5)MCLR GPA67N IOCN GPA76N SCLIOCN GPB010N SDAIOCN GPB126 YAN4 IOCY Error Signal In/Out (3)GPB228 YAN5 IOCY GPB44 YAN6 IOCYICSPDATICDDAT GPB527 YAN7 IOCYICSPCLKICDCLKA lternate Sync Signal In/Out (2, 3)GPB621N IOCY GPB711N IOCY VIN13N VIND evice Input VoltageVDR16N VDRGate Drive Supply Input VoltageVDD20N VDDI nternal Regulator Output GND12N GNDS mall Signal GroundPGND14N Large Signal GroundLDRV15N Low-Side MOSFETC onnectionHDRV18N High-Side MOSFETC onnectionPHASE17N Switch NodeBOOT19N Floating Bootstrap Supply+VSEN24N Output Voltage Differential Sense-VSEN25N Output Voltage Differential Sense+ISEN23N Current Sense Input-ISEN22N Current Sense InputNote 1:The Analog Debug Output is selected when the ATSTCON<BNCHEN> bit is :Selected when the device is functioning as multiple output master or slave by proper configuration of the MLTPH<2:0> bits in the BUFFCON :Selected when the device is functioning as multi-phase master or slave by proper configuration of the MLTPH<2:0> bits in the BUFFCON :The IOC is disabled when MCLR is :Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.

5 mcp19118 /19DS20005350A-page 6 2014 Microchip Technology of Overview .. Description .. Description .. Characteristics .. Electrical Characteristics .. the MCP19118/19 .. Performance Curves .. Bench Testing .. Calibration .. Relative Efficiency Measurement .. Memory Organization .. Device Configuration .. Oscillator Resets .. Interrupts .. Power-Down Mode (Sleep) .. Watchdog Timer (WDT).. Flash Program Memory Control .. I/O Ports .. Interrupt-on-Change .. Internal Temperature Indicator Analog-to-Digital Converter (ADC) Module .. Timer0 Timer1 Module with Gate Control .. Timer2 PWM Module .. Master Synchronous Serial Port (MSSP) Module .. In-Circuit Serial Programming (ICSP ) .. Instruction Set Summary .. Development Packaging 207 Appendix A: Revision 213 Index.

6 215 The Microchip Web Site .. 221 Customer Change Notification Service .. 221 Customer Support .. 221 Product Identification 223 2014 Microchip Technology 7 mcp19118 /19TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at We welcome your Current Data SheetTo obtain the most up-to-date version of this data Sheet , please register at our Worldwide Web site at: can determine the version of a data Sheet by examining its literature number found on the bottom outside corner of any last character of the literature number is the version number, ( , DS30000000A is version A of document DS30000000).

7 ErrataAn errata Sheet , describing minor operational differences from the data Sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata Sheet . The errata will specify the revisionof silicon and revision of document to which it determine if an errata Sheet exists for a particular device, please check with one of the following: Microchip s Worldwide Web site; Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data Sheet (include literature number) you Notification SystemRegister on our web site at to receive the most current information on all of our 8 2014 Microchip Technology : 2014 Microchip Technology 9 mcp19118 OVERVIEWThe MCP19118/19 is a highly integrated, mixed signal,analog pulse-width modulation (PWM) current modecontroller with an integrated microcontroller core forsynchronous DC/DC step-down applications.

8 Since theMCP19118/19 uses traditional analog control circuitryto regulate the output of the DC/DC converter, theintegration of the PIC microcontroller mid-range coreis used to provide complete customization of deviceoperating parameters, start-up and shutdown profiles,protection levels and fault handling MCP19118/19 is designed to efficiently operatefrom a single to 40V supply. It features integratedsynchronous drivers, bootstrap device, internal linearregulator and 4 kW nonvolatile memory, all in aspace-saving 24-pin 4 mm x 4 mm QFN package( mcp19118 ) or 28-pin 5 mm x 5 mm QFN package(MCP19119).After initial device configuration using Microchip sMPLAB X Integrated Development Environment (IDE)software, the PMBus or I2C can be used by a host tocommunicate with, or modify, the operation of theMCP19118/19.

9 Two internal linear regulators generate two 5V 5V rail is used to provide power for the internalanalog circuitry and is contained on-chip. The second5V rail provides power to the PIC device and is presenton the VDD pin. It is recommended that a 1 F capacitorbe placed between VDD and PGND. The VDD pin mayalso be directly connected to the VDR pin or connectedthrough a low-pass RC filter. The VDR pin providespower to the internal synchronous 1-1:TYPICAL APPLICATION CIRCUITBOOTHDRVLDRVPHASE+ISEN-ISEN+VSEN- VSENVINVDDVDRVPGNDGNDMCP19118/9 VINVOUTGPIO9 (13)SDASCLI2 CMCP19118/19DS20005350A-page 10 2014 Microchip Technology 1-2: MCP19118/19 SYNCHRONOUS BUCK BLOCK DIAGRAMPHASEHDRVLDRVVINVDDBOOTVINVOUTVDA CAVDDLDO1 LDO2 Bias GenBGAPUVLO44 VZC5 SlaveModeMasterModeVREGREFUV REFOV REF8+588 VOUTVOUTVOUTOVUVBGAPLo_on4 AVDDVDD5 OCCompVINDLY4 LVL_SFTPIC CORED ebugMUXLo_onBuckOVUVVIN_OKOCFLAGA/D MuxVDR-ISEN+VSEN-VSEN+ISEN+ISEN-ISEN+VSE N-VSENGNDPGNDI/O(Digital Signals)I/OI/O6R5 RVDRDLY443To ADCCSDGENbitDC current sense gainAC current sense gain11 (15) 2014 Microchip Technology 11 MCP19118/19 FIGURE 1-3.

10 MICROCONTROLLER CORE BLOCK DIAGRAMF lashProgramMemory13 Data Bus814 ProgramBusInstruction regProgram CounterRAMFileRegistersDirect Addr7 RAM Addr 9 Addr MUXI ndirectAddrFSR regSTATUS regMUXALUW regInstructionDecode &ControlTimingGenerationTESTCLKINPORTA88 838 Level Stack2564K x 14 bytes(13-bit)Power-upTimerPower-onResetW atchdogTimerMCLRVIN VSST imer0 Timer1T0 CKIC onfiguration8 MHz InternalOscillatorTimer2 MSSPGPA0 GPA1 GPA2 GPA3 GPA4 GPA5 Analog InterfaceSDASCLPMDATLEEADDRSelf read/ write flashmemoryRegistersPORTBGPB0 GPB1 GPB2 GPB6 (MCP19119)GPB4 (MCP19119)PWMGPB5 (MCP19119)GPA6 GPA7 GPB7 (MCP19119) mcp19118 /19DS20005350A-page 12 2014 Microchip Technology DESCRIPTIONThe MCP19118/19 family of devices features pins thathave multiple functions associated with each 2-1 provides a description of the differentfunctions. See Section Detailed Pin FunctionalDescription for more detailed 2-1.