Packet Accelerator (PA) for KeyStone Devices User's …

1 KeyStone Architecture Packet Accelerator (PA). User Guide Literature Number: SPRUGS4A. July 2012. Release History Release Date Description/Comments SPRUGS4A July 2012 Added Clock Control section (Page 2-2). Added Packet Accelerator Queue Interface Section. (Page 2-2). Added Programming the Packet Accelerator with the Low-Level Driver section. (Page 2-2). Added the L4 Classify Engine Architecture section. (Page 2-4). Added the L3 Classify Engine Architecture section. (Page 2-4). Added the L2 Classify Engine Architecture section. (Page 2-4). Added the Modify/Multiroute Engine Architecture section. (Page 2-5). Removed the PDSP, LUT1, LUT2, and Timer Architecture sections. (Page 2-6). Updated Receive classification dataflow example. (Page 3-2). Updated transmit checksum generation dataflow example. (Page 3-3). Added Power Management Section (Page 2-6).

2 Corrected the number of receive channels from 26 to 24 (Page 1-2). SPRUGS4 November 2010 Initial Release -ii KeyStone Architecture Packet Accelerator (PA) User Guide SPRUGS4A July 2012. Submit Documentation Feedback Contents Contents Release History.. -ii List of Tables .. -v List of Figures .. -vi Preface -vii About This Manual.. -vii Notational Conventions .. -vii Related Documentation from Texas Instruments .. -viii Trademarks .. -viii Chapter 1. Introduction 1-1. Purpose of the Peripheral .. 1-2. Features .. 1-2. Functional Block Diagram .. 1-3. Chapter 2. Architecture 2-1. Clock Control .. 2-2. Packet Accelerator Transmit Queue Interface .. 2-2. Programming the Packet Accelerator with the Low-Level Driver .. 2-2. L2 Classify Engine Architecture .. 2-4. L3 Classify Engine Architecture .. 2-4. L4 Classify Engine Architecture.

3 2-4. Modify/Multiroute Engine Architecture .. 2-5. Adding Entries to the Classification Engines.. 2-5. DMA Event Support .. 2-6. Power Management .. 2-6. Chapter 3. Data Flow Examples 3-1. Overview .. 3-2. Receive Classification Example .. 3-2. Transmit Checksum Generation Example .. 3-3. Chapter 4. Registers 4-1. PDSP Mailbox Slots .. 4-3. Packet ID Allocation Registers .. 4-4. Packet ID Revision Register (PID_REV).. 4-4. Packet ID Allocation Module Soft Reset Register (PID_SOFT_RESET) .. 4-4. Packet ID Allocation Module Range Limit Register (PID_RANGE_LIM) .. 4-4. Packet ID Allocation Module ID Value Register (PID_IDVAL).. 4-5. Stage 2 Look Up Table (LUT2) Control Registers Region .. 4-6. LUT2 Revision Register (REV) .. 4-6. LUT2 Soft Reset Register (LUT2_SOFT_RESET) .. 4-6. Add Data 0 Register (ADD_DATA0) .. 4-7. SPRUGS4A July 2012 KeyStone Architecture Packet Accelerator (PA) User Guide -iii Submit Documentation Feedback Contents Add Data 1 Register (ADD_DATA1).

4 4-7. Add Data 2 Register (ADD_DATA2) .. 4-7. Add Data 3 Register .. 4-7. Add/Delete Key Register (ADD_DEL_KEY) .. 4-7. Add/Delete Control Register (ADD_DEL_CONTROL) .. 4-8. PDSP Control/Status Register Region .. 4-9. PDSP Control Register (PDSP_CONTROL).. 4-9. PDSP Status Register ..4-10. PDSP Wakeup Enable Register (PDSP_WAKE_EN)..4-10. PDSP Cycle Count Register (PDSP_CYCLECOUNT) ..4-11. PDSP Stall Count Register (PDSP_STALLCOUNT)..4-11. PDSP Constant Table Block Index Register 0 (PDSP_BLK_IDX0)..4-11. PDSP Constant Table Block Index Register 1 (PDSP_BLK_IDX1)..4-12. PDSP Constant Table Programmable Pointer Register 0 (PDSP_POINTER0) ..4-12. PDSP Constant Table Programmable Pointer Register 1 (PDSP_POINTER1) ..4-12. PDSP Timer Registers ..4-13. Control Timer Register (CNTL_TIM) ..4-13. Load Timer Register (LOAD_TIM) ..4-14.

5 Value Timer Register (VALUE_TIM) ..4-14. Timer Interrupt Register (TIMER_IRQ) ..4-14. Packet Accelerator Statistics Register Region..4-15. Revision Register..4-15. Soft Reset Register ..4-15. Increment Flags Register ..4-16. Statistics Capture Register..4-16. Statistic N Register ..4-16. Index IX-1. -iv KeyStone Architecture Packet Accelerator (PA) User Guide SPRUGS4A July 2012. Submit Documentation Feedback List of Tables List of Tables Table 2-1 Queue to PA Engine Mapping.. 2-2. Table 2-2 SA LLD APIs .. 2-3. Table 4-1 Packet Accelerator Memory Map.. 4-2. Table 4-2 PDSP Mailbox Slots .. 4-3. Table 4-3 Packet ID Allocation Registers.. 4-4. Table 4-4 Packet ID Allocation Module Revision Register (PID_REV) .. 4-4. Table 4-5 Packet ID Allocation Module Soft Reset Register (PID_SOFT_RESET) .. 4-4. Table 4-6 Packet ID Allocation Module Range Limit Register (PID_RANGE_LIM).

6 4-4. Table 4-7 Packet ID Allocation Module IdValue Register (PID_IDVAL) .. 4-5. Table 4-8 LUT2 Control Registers Region memory Map .. 4-6. Table 4-9 LUT2 Revision Register (REV) .. 4-6. Table 4-10 LUT2 Soft Reset Register (LUT2_SOFT_RESET) .. 4-6. Table 4-11 Add Data 0 Register (ADD_DATA0).. 4-7. Table 4-12 Add Data 1 Register (ADD_DATA1).. 4-7. Table 4-13 Add Data 2 Register (ADD_DATA2).. 4-7. Table 4-14 Add Data 3 Register (ADD_DATA3).. 4-7. Table 4-15 Add/Delete Key Register (ADD_DEL_KEY) .. 4-7. Table 4-16 Add/Delete Control Register (ADD_DEL_CONTROL) .. 4-8. Table 4-17 PDSP Control/Status Register Region.. 4-9. Table 4-18 PDSP Control Register (PDSP_CONTROL) .. 4-9. Table 4-19 PDSP Status Register (PDSP_STATUS) .. 4-10. Table 4-20 PDSP Wakeup Enable Register (PDSP_WAKE_EN) .. 4-10. Table 4-21 PDSP Cycle Count Register (PDSP_CYCLECOUNT).

7 4-11. Table 4-22 PDSP Stall Count Register (PDSP_STALLCOUNT) .. 4-11. Table 4-23 PDSP Constant Table Block Index Register 0 (PDSP_BLK_IDX0) .. 4-11. Table 4-24 PDSP Constant Table Block Index Register 1 (PDSP_BLK_IDX1) .. 4-12. Table 4-25 PDSP Constant Table Programmable Pointer Register 0 (PDSP_POINTER0) .. 4-12. Table 4-26 PDSP Constant Table Programmable Pointer Register 1 (PDSP_POINTER1) .. 4-12. Table 4-27 PDSP Timer Registers .. 4-13. Table 4-28 Control Timer Register (CNT_TIM) .. 4-13. Table 4-29 Load Timer Register (LOAD_TIM).. 4-14. Table 4-30 Value Timer Register (VALUE_TIM) .. 4-14. Table 4-31 Timer Interrupt Register (TIMER_IRQ).. 4-14. Table 4-32 Packet Accelerator Statistics Register Region Memory Map .. 4-15. Table 4-33 Revision Register .. 4-15. Table 4-34 Soft Reset Register .. 4-15. Table 4-35 Increment Flags Register.

8 4-16. Table 4-36 Statistics Capture Register .. 4-16. Table 4-37 Statistics N Register.. 4-16. SPRUGS4A July 2012 KeyStone Architecture Packet Accelerator (PA) User Guide -v Submit Documentation Feedback List of Figures List of Figures Figure 1-1 Packet Accelerator Functional Block Diagram .. 1-3. Figure 3-1 Receive Classification Example .. 3-2. Figure 3-2 Transmit Checksum Generation Example.. 3-3. -vi KeyStone Architecture Packet Accelerator (PA) User Guide SPRUGS4A July 2012. Submit Documentation Feedback Preface About This Manual The Packet Accelerator (PA) is one of the main components of the network coprocessor (NETCP) peripheral. The PA works together with the security Accelerator (SA) and the gigabit Ethernet switch subsystem to form a network processing solution. The purpose of PA in the NETCP is to perform Packet processing operations such as Packet header classification, checksum generation, and multi-queue routing.

9 Notational Conventions This document uses the following conventions: Commands and keywords are in boldface font. Arguments for which you supply values are in italic font. Terminal sessions and information the system displays are in screen font. Information you must enter is in boldface screen font. Elements in square brackets ([ ]) are optional. Notes use the following conventions: Note Means reader take note. Notes contain helpful suggestions or references to material not covered in the publication. The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. CAUTION Indicates the possibility of service interruption if precautions are not taken. WARNING Indicates the possibility of damage to equipment if precautions are not taken. SPRUGS4A July 2012 KeyStone Architecture Packet Accelerator (PA) User Guide -vii Submit Documentation Feedback Preface Related Documentation from Texas Instruments Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide SPRUGV9.

10 Interrupt Controller (INTC) for KeyStone Devices User Guide SPRUGW4. Multicore Navigator for KeyStone Devices User Guide SPRUGR9. Network Coprocessor (NETCP) for KeyStone Devices User Guide SPRUGZ6. Security Accelerator (SA) for KeyStone Devices User Guide SPRUGY6. Trademarks TMS320C66x and C66x are trademarks of Texas Instruments Incorporated. All other brand names and trademarks mentioned in this document are the property of Texas Instruments Incorporated or their respective owners, as applicable. -viii KeyStone Architecture Packet Accelerator (PA) User Guide SPRUGS4A July 2012. Submit Documentation Feedback Chapter 1. Introduction "Purpose of the Peripheral" on page 1-2. "Features" on page 1-2. "Functional Block Diagram" on page 1-3. SPRUGS4A July 2012 KeyStone Architecture Packet Accelerator (PA) User Guide 1-1. Submit Documentation Feedback Purpose of the Peripheral Chapter 1 Introduction Purpose of the Peripheral The Packet Accelerator (PA) is one of the main components of the network coprocessor (NETCP) peripheral.