PIC18(L)F27/47K40 Data Sheet - Microchip Technology

1 pic18 (L)F27/ 47k40 28/40/44-Pin, Low-Power, High-PerformanceMicrocontrollers with XLP TechnologyDescriptionThese pic18 (L)F27/ 47k40 microcontrollers feature analog, core independent peripherals andcommunication peripherals, combined with eXtreme Low-Power (XLP) Technology for a wide range ofgeneral purpose and low-power applications. These 28/40/44 -pin devices are equipped with a 10-bitADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advancedtouch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. Theyalso offer a set of core independent peripherals such as Complementary Waveform Generator (CWG),Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-CrossDetect (ZCD) and Peripheral Pin Select (PPS) providing for increased design flexibility and lower Features C Compiler Optimized RISC Architecture Operating Speed.

2 DC 64 MHz clock input over the full VDD range ns minimum instruction cycle Programmable 2-Level Interrupt Priority 31-Level Deep Hardware Stack Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT) Four 16-Bit Timers (TMR0/1/3/5) Low-Current Power-on Reset (POR) Power-up Timer (PWRT) Brown-out Reset (BOR) Low-Power BOR (LPBOR) Option Windowed Watchdog Timer (WWDT): Watchdog Reset on too long or too short interval between watchdog clear events Variable prescaler selection Variable window size selection All sources configurable in hardware or softwareMemory 128K Bytes Program Flash Memory 3728 Bytes data SRAM Memory 2018 Microchip Technology Inc.

3 DatasheetDS40001844E-page 1 1024 Bytes data EEPROM Programmable Code Protection Direct, Indirect and Relative Addressing modesOperating Characteristics Operating Voltage Ranges: to (PIC18LF27/ 47k40 ) to ( PIC18F27/ 47k40 ) Temperature Range: Industrial: -40 C to 85 C Extended: -40 C to 125 CPower-Saving Operation Modes Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower) Idle: CPU Halted While Peripherals Operate Sleep: Lowest Power Consumption Peripheral Module Disable (PMD): Ability to selectively disable hardware module to minimize active power consumption of unusedperipherals Extreme Low-Power mode (XLP) Sleep: 500 nA typical @ Sleep and Watchdog Timer: 900 nA typical @ Low-Power (XLP) Features Sleep mode: 50 nA @ , typical Windowed Watchdog Timer: 500 nA @ , typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: 8 uA @ 32 kHz, , typical 32 uA/MHz @ , typicalDigital Peripherals Complementary Waveform Generator (CWG): Rising and falling edge dead-band control Full-bridge, half-bridge, 1-channel drive Multiple signal sources Capture/Compare/PWM (CCP) modules.

4 Two CCPs 16-bit resolution for Capture/Compare modes 10-bit resolution for PWM mode 10-Bit Pulse-Width Modulators (PWM): pic18 (L)F27/ 47k40 2018 Microchip Technology Inc. DatasheetDS40001844E-page 2 Two 10-bit PWMs serial Communications: Two Enhanced USART (EUSART) with Auto-Baud Detect, Auto-wake-up on Start. RS-232, RS-485, LIN compatible SPI I2C, SMBus and PMBus compatible Up to 35 I/O Pins and One Input Pin: Individually programmable pull-ups Slew rate control Interrupt-on-change on all pins Input level selection control Programmable CRC with Memory Scan: Reliable data /program memory monitoring for Fail-Safe operation ( , Class B) Calculate CRC over any portion of Flash or EEPROM High-speed or background operation Hardware Limit Timer (TMR2/4/6+HLT): Hardware monitoring and Fault detection Peripheral Pin Select (PPS).

5 Enables pin mapping of digital I/O data Signal Modulator (DSM)Analog Peripherals 10-Bit Analog-to-Digital Converter with Computation (ADC2): 35 external channels Conversion available during sleep Four internal analog channels Internal and external trigger options Automated math functions on input signals: Averaging, filter calculations, oversampling and threshold comparison 8-bit hardware acquisition timer Hardware Capacitive Voltage Divider (CVD) Support: 8-bit precharge timer Adjustable sample and hold capacitor array Guard ring digital output drive Zero-Cross Detect (ZCD): Detect when AC signal on pin crosses ground 5-Bit Digital-to-Analog Converter (DAC): Output available externally Programmable 5-bit voltage (% of VDD,[VRef+ - VRef-], FVR) Internal connections to comparators and ADC Two Comparators (CMP): Four external inputs External output via PPS pic18 (L)F27/ 47k40 2018 Microchip Technology Inc.

6 DatasheetDS40001844E-page 3 Fixed Voltage Reference (FVR) Module: , and output levels Two buffered outputs: One for DAC/CMP and one for ADCC locking Structure High-Precision Internal Oscillator Block (HFINTOSC): Selectable frequencies up to 64 MHz 1% at calibration 32 kHz Low-Power Internal Oscillator (LFINTOSC) External 32 kHz Crystal Oscillator (SOSC) External High-frequency Oscillator Block: Three crystal/resonator modes Digital Clock Input mode 4x PLL with external sources Fail-Safe Clock Monitor: Allows for safe shutdown if external clock stops Oscillator Start-up Timer (OST)Programming/Debug Features In-Circuit serial Programming (ICSP ) via Two Pins In-Circuit Debug (ICD) with Three Breakpoints via Two Pins Debug Integrated On-ChipPIC18(L)F27/ 47k40 Family TypesTable 1.

7 Devices included in this data sheetDeviceProgram Memory Flash(bytes) data SRAM(bytes) data EEPROM(bytes)I/O Pins16-bit TimersComparators10-bit ADC2 withComputation (ch)5-bit DACZero-Cross DetectCCP/10-bit PWMCWGSMTLow Voltage Detect (LVD)8-bit TMR with HLTW indowed WatchdogTimerCRC with Memory ScanEUSARTI2C/SPIPPSP eripheral Module DisableTemperature IndicatorDebug(1) pic18 (L)F27K40128k36151 024254224112/21013YY22 YYYIPIC18(L)F47K40128k36151024364235112/ 21013YY22 YYYI pic18 (L)F27/ 47k40 2018 Microchip Technology Inc. DatasheetDS40001844E-page 4 Table 2. Devices not included in this data sheetDeviceProgram Memory Flash(bytes) data SRAM(bytes) data EEPROM(bytes)I/O Pins16-bit TimersComparators10-bit ADC2 withComputation (ch)5-bit DACZero-Cross DetectCCP/10-bit PWMCWGSMTLow Voltage Detect (LVD)8-bit TMR with HLTW indowed WatchdogTimerCRC with Memory ScanEUSARTI2C/SPIPPSP eripheral Module DisableTemperature IndicatorDebug(1) pic18 (L)F24K4016k102425 6254224112/21013YY11 YYYIPIC18(L)F25K4032k2048256254224112/21 013YY11 YYYIPIC18(L)F26K4064k36151024254224112/2 1013YY22 YYYIPIC18(L)F45K4032k2048256364235112/21 013YY22 YYYIPIC18(L)F46K4064k36151024364235112/2 1013YY22 YYYIPIC18(L)

8 F65K4032k20481024605345115/21214YY52 YYYIPIC18(L)F66K4064k35621024605345115/2 1214YY52 YYYIPIC18(L)F67K40128k35621024605347115/ 21214YY52 YYYINote: Debugging Methods: (I) Integrated on Sheet Index:1. DS40001843 pic18 (L)F24/25K40 data Sheet , 28-Pin, 8-bit Flash Microcontrollers2. DS40001816 pic18 (L)F26/45/46K40 data Sheet , 28/40/44-Pin, 8-bit Flash Microcontrollers3. DS40001844 pic18 (L)F27/ 47k40 data Sheet , 28/40/44-Pin, 8-bit Flash Microcontrollers4. DS40001842 pic18 (L)F65/66K40 data Sheet , 64-Pin, 8-bit Flash Microcontrollers5. DS40001841 pic18 (L)F67K40 data Sheet , 64-Pin, 8-bit Flash MicrocontrollersPin DiagramsFigure 1. 28-pin SPDIP, SSOP, : 28-pin DIPLast Edit:3/6/2017 First Used:N/ANotes:Generic 28-pin dual in-line diagramRev.

9 00-000 028A3/6/201 7 MCLR/VPP/RE32827262524232221201918171615 1413121110987654321RA0RA1RA2RA3RA4RA5 VSSRA7RA6RC0RC1RC2RC3RC4RC5RC6RC7 VSSVDDRB0RB1RB2RB3RB4RB6RB6/ICSPCLKRB7/I CSPDAT pic18 (L)F27/ 47k40 2018 Microchip Technology Inc. DatasheetDS40001844E-page 5 Figure 2. 28-pin QFNRev. 00-000028B6/23/201728 27RB3RB2RC7RB5RB4 VSSRB1RB0 VDDRB6/ICSPCLKRB7/ICSPDATRE3/MCLR/VPPRA0 RA126 25 24 23 228 9 10 11 12 13 14151617181920217654321RC5RC6RC4RC3RC2RC 1RC0RA2RA3RA6RA7RA4RA5 VSSNote: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the onlyVSS connection to the 3. 40-pin : 40-pin DIPLast Edit:3/6/2017 First Used:N/ANotes:Generic 40-pin dual in-line diagramRev.

10 00-000 040A3/6/201 7 MCLR/VPP/RE34039383736353433323130292827 1413121110987654321RA0RA1RA2RA3RA4RA5 VSSRA7RA6RC0RC1RC2RC3RD4RD5RD6RD7 VSSVDDRB0RB1RB2RB3RB4RB6RB6/ICSPCLKRB7/I CSPDAT151617181920262524232221RD0RD1 VDDRE0RE1RE2RD2RD3RC4RC5RC6RC7 pic18 (L)F27/ 47k40 2018 Microchip Technology Inc. DatasheetDS40001844E-page 6 Figure 4. 40-pin : 40-pin QFNLast Edit:11/6/2017 First Used:N/ANotes:Generic 40-pin QFN diagramRev. 00-000040B11/6/20174039RC0RA6RE1RE0RA5RA 4RC1RC2RC3RD1RD0RE2RA7 VSSVDDRD2RD3RC4RC5RC63837363534333231111 2131415161718192021222324252627282930109 87654321RA3RA2RA1 VPP/MCLR/RE3RA0 ICSPDAT/RB7 ICSPCLK/RB6RB5RB4RB3RC7RD4 VDDRB0RB1RB2 VSSRD5RD6RD7 Note: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the onlyVSS connection to the 5.