PM0214 Programming manual - STMicroelectronics

1 October 2017 DocID022708 Rev 61/2601PM0214 Programming manualSTM32F3 Series, STM32F4 Series, STM32L4 Series and STM32L4+ Series Cortex -M4 Programming manualIntroductionThis Programming manual provides information for application and system-level software developers. It gives a full description of the STM32 Cortex -M4 processor Programming model, instruction set and core STM32F3 Series, STM32F4 Series, STM32L4 Series and STM32L4+ Series Cortex -M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including: Outstanding processing performance combined with fast interrupt handling Enhanced system debug with extensive breakpoint and trace capabilities Efficient processor core, system and memories Ultra-low power consumption with integrated sleep modes Platform securityReference documentsAvailable from STMicroelectronics web site : STM32F3 Series, STM32F4 Series, STM32L4 Series and STM32L4+ Series datasheets STM32F3 Series, STM32F4 Series, STM32L4 Series and STM32L4+ Series reference Rev 6 Contents1 About this document.

2 Conventions .. of abbreviations for registers .. the STM32 Cortex-M4 processor and core peripherals .. level interface .. configurable debug .. processor features and benefits summary .. core peripherals .. 152 The Cortex-M4 processor .. model .. mode and privilege levels for software execution .. registers .. and interrupts .. types .. Cortex microcontroller software interface standard (CMSIS) .. model .. regions, types and attributes .. system ordering of memory accesses .. of memory accesses .. ordering of memory accesses .. endianness .. primitives .. hints for the synchronization primitives .. model .. states .. types .. handlers .. table .. priorities .. priority grouping .. entry and return .. 41 DocID022708 Rev 63 handling .. types .. escalation and hard faults .. status registers and fault address registers.

3 Management .. sleep mode .. from sleep mode .. event input / extended interrupt and event input .. management Programming hints .. 483 The STM32 Cortex-M4 instruction set .. set summary .. intrinsic functions .. the instruction descriptions .. when using PC or SP .. second operand .. operations .. alignment .. expressions .. execution .. width selection .. access instructions .. and STR, immediate offset .. and STR, register offset .. and STR, unprivileged .. , PC-relative .. and STM .. and POP .. and STREX .. data processing instructions .. , ADC, SUB, SBC, and RSB .. , ORR, EOR, BIC, and ORN .. 84 ContentsPM02144/260 DocID022708 Rev , LSL, LSR, ROR, and RRX .. and CMN .. and MVN .. , REV16, REVSH, and RBIT .. and SADD8 .. and SHADD8 .. and SHSAX .. and SHSUB8 .. and SSUB8 .. and SSAX .. and TEQ.

4 And UADD8 .. and USAX .. and UHADD8 .. and UHSAX .. and UHSUB8 .. and USUB8 .. and divide instructions .. , MLA, and MLS .. , UMAAL and UMLAL .. and SMLAW .. and SMLALD .. and SMLSLD .. and SMMLS .. and SMUSD .. and SMULW .. , UMLAL, SMULL, and SMLAL .. and UDIV .. instructions .. and USAT .. 125 DocID022708 Rev 65 and USAT16 .. and QSUB .. and QSAX .. and QDSUB .. and UQSAX .. and UQSUB .. and unpacking instructions .. and PKHTB .. and UXT .. and UXTA .. instructions .. and BFI .. and UBFX .. and UXT .. and control instructions .. , BL, BX, and BLX .. and CBNZ .. and TBH .. instructions .. , VCMPE .. , VCVTR between floating-point and integer .. between floating-point and fixed-point .. , VCVTT .. , VFMS .. , VFNMS .. VLDM .. VLDR .. VLMA, VLMS .. VMOV immediate.

5 VMOV register .. VMOV scalar to ARM core register .. VMOV ARM core register to single precision .. VMOV two ARM core registers to two single precision .. 166 ContentsPM02146/260 DocID022708 Rev VMOV ARM Core register to scalar .. VMRS .. VMSR .. VMUL .. VNEG .. VNMLA, VNMLS, VNMUL .. VPOP .. VPUSH .. VSQRT .. VSTM .. VSTR .. VSUB .. instructions .. SVC .. WFE .. WFI .. 1914 Core peripherals .. the STM32 Cortex-M4 core peripherals .. protection unit (MPU) .. access permission attributes .. mismatch .. an MPU region .. design hints and tips .. type register (MPU_TYPER) .. control register (MPU_CTRL) .. region number register (MPU_RNR) .. region base address register (MPU_RBAR) .. 202 DocID022708 Rev 67 region attribute and size register (MPU_RASR) .. register map.

6 Vectored interrupt controller (NVIC) .. the Cortex-M4 NVIC registers using CMSIS .. set-enable registers (NVIC_ISERx) .. clear-enable registers (NVIC_ICERx) .. set-pending registers (NVIC_ISPRx) .. clear-pending registers (NVIC_ICPRx) .. active bit registers (NVIC_IABRx) .. priority registers (NVIC_IPRx) .. trigger interrupt register (NVIC_STIR) .. and pulse interrupts .. design hints and tips .. register map .. control block (SCB) .. control register (ACTLR) .. base register (CPUID) .. control and state register (ICSR) .. table offset register (VTOR) .. interrupt and reset control register (AIRCR) .. control register (SCR) .. and control register (CCR) .. handler priority registers (SHPRx) .. handler control and state register (SHCSR) .. fault status register (CFSR; UFSR+BFSR+MMFSR) .. fault status register (UFSR) .. fault status register (BFSR).

7 Management fault address register (MMFSR) .. fault status register (HFSR) .. management fault address register (MMFAR) .. fault address register (BFAR) .. fault status register (AFSR) .. control block design hints and tips .. register map .. timer (STK) .. control and status register (STK_CTRL) .. reload value register (STK_LOAD) .. 247 ContentsPM02148/260 DocID022708 Rev current value register (STK_VAL) .. calibration value register (STK_CALIB) .. design hints and tips .. register map .. point unit (FPU) .. access control register (CPACR) .. context control register (FPCCR) .. context address register (FPCAR) .. status control register (FPSCR) .. default status control register (FPDSCR) .. the FPU .. and clearing FPU exception interrupts .. 2575 Revision history .. 259 DocID022708 Rev 69/260PM0214 List of tables10 List of tablesTable of processor mode, execution privilege level, and stack usage.

8 17 Table register set summary .. 17 Table register combinations .. 19 Table bit definitions .. 20 Table bit definitions .. 21 Table bit definitions .. 22 Table register bit definitions.. 23 Table register bit definitions .. 23 Table register bit assignments .. 24 Table register bit definitions .. 24 Table of memory accesses .. 28 Table access behavior .. 29 Table memory bit-banding regions .. 31 Table memory bit-banding regions .. 31 Table functions for exclusive access instructions.. 35 Table of the different exception types .. 37 Table return behavior .. 43 Table .. 44 Table status and fault address registers .. 46 Table instructions .. 49 Table intrinsic functions to generate some Cortex-M4 instructions .. 58 Table intrinsic functions to access the special registers.. 58 Table code suffixes.. 66 Table access instructions .. 68 Table , pre-indexed and post-indexed offset ranges.

9 71 Table offset ranges .. 74 Table processing instructions.. 80 Table and divide instructions .. 108 Table instructions .. 124 Table and unpacking instructions .. 133 Table that operate on adjacent sets of bits.. 137 Table and control instructions .. 141 Table ranges .. 142 Table instructions .. 148 Table instructions .. 179 Table core peripheral register regions .. 192 Table attributes summary .. 193 Table , C, B, and S encoding .. 194 Table policy for memory attribute encoding .. 194 Table encoding .. 195 Table region attributes for STM32 .. 198 Table SIZE field values .. 204 Table register map and reset values .. 205 Table register summary .. 207 Table access NVIC functions .. 208 Table bit assignments .. 214 Table functions for NVIC control .. 217 Table register map and reset values .. 218 List of tablesPM021410/260 DocID022708 Rev 6 Table of the system control block registers.

10 220 Table grouping .. 228 Table fault handler priority fields .. 232 Table register map and reset values .. 243 Table timer registers summary .. 245 Table register map and reset values .. 250 Table floating-point system registers .. 251 Table of a Floating-point comparison on the condition flags .. 255 Table revision history .. 259 DocID022708 Rev 611/260PM0214 List of figures11 List of figuresFigure Cortex-M4 implementation .. 13 Figure core registers .. 17 Figure , IPSR and EPSR bit assignments .. 19 Figure bit assignments .. 19 Figure bit assignments .. 23 Figure bit assignments .. 23 Figure bit assignments .. 24 Figure map .. 27 Figure mapping .. 32 Figure example .. 33 Figure table.. 39 Figure stack frame layout .. 42 Figure #3 .. 61 Figure #3 .. 62 Figure #3 .. 62 Figure #3 .. 63 Figure #3 .. 63 Figure example .. 197 Figure register mapping.