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Power Supply Design Considerations for Modern …

Power designer Expert tips, tricks, and techniques for powerful designs No. 121 Power Supply Design Considerations for Modern FPGAs By Dennis Hudgins, Low Voltage Applications Manages, Tucson Design Center Introduction Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, Power Supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, Power -on, and soft-start requirements can result in unreliable Power -up or potential damage to FPGAs. Output Voltage Requirements The rst criteria to consider when designing Power supplies for FPGAs are the voltage requirements for the di erent Supply rails.

4 POWER designer Power Supply Design Considerations for Modern FPGAs Th e critical area for monitonicity for most modern core voltage rails occurs between 0.5V to …

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Transcription of Power Supply Design Considerations for Modern …

1 Power designer Expert tips, tricks, and techniques for powerful designs No. 121 Power Supply Design Considerations for Modern FPGAs By Dennis Hudgins, Low Voltage Applications Manages, Tucson Design Center Introduction Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, Power Supply requirements may be more demanding, requiring special attention to features deemed less important in past generations. Failure to consider the output voltage, sequencing, Power -on, and soft-start requirements can result in unreliable Power -up or potential damage to FPGAs. Output Voltage Requirements The rst criteria to consider when designing Power supplies for FPGAs are the voltage requirements for the di erent Supply rails.

2 Most FPGAs have speci cations for the CORE and IO voltage rails and many require additional auxiliary rails that may Power internal clocks, phase-lock loops or transceivers. Table 1 provides the voltage levels and tolerances for some of the newest FPGAs. Table 1. Voltage Requirements for Common Modern FPGAs FPGA Core Core Tolerance Auxiliary Power Auxiliary Tolerance IO Voltage* IO Tolerance*. Spartan-6 5% or 5% to to Spartan-6 (-1L) 5% or 5% to to Virtex-6 5% 5% to to Virtex-6 (-1L) 30 mV 5% to to Stratix-IV (GX and E) 30 mV (VCCA_PLL) 5% to 5%. (VCCD_PLL) 30 mV. Stratix-IV (GT) 30 mV (VCCA_PLL) 5% to 5%. (VCCD_PLL) 30 mV. Cyclone-IV (GX) 40 mV 5% to 5%.

3 Cyclone-IV (E) * 5% to 5%. Arria-II 30 mV (VCCA_PLL) 5% to 5%. (VCCD_PLL) 30 mV. * Some values may differ slightly from those listed. Please consult your FPGA's associated documentation for details. Power designer Power Supply Design Considerations for Modern FPGAs Since FPGAs generally specify several permissible The response to a load transient is dictated by the voltage levels for the IO, the voltage selected is dictated large signal response time that consists of ramping the by the external digital circuitry. To provide exibility, inductor current to the correct operating level and the FPGAs will generally provide multiple IO banks that small signal response of the control loop.

4 Can be powered separately, allowing FPGAs to Transient Response Optimizations interface with various logic families. For simplicity, To optimize the transient response, ensure the Supply the solutions illustrated in this article will assume all is switching at the highest possible frequency. This IO banks are powered o of a single Power Supply rail. will allow use of a small inductor and reduce the large The core voltage supplies the internal logic signal response time. Typical high performance Power con guration blocks of FPGAs and is where many of Supply solutions can be designed to have crossover the internal digital path processes occur. As such, the frequencies as high as one-tenth to one- fth the current demanded by the core will vary greatly switching frequency.

5 Pushing the crossover frequency depending on the percent utilization of FPGAs. too high may result in ringing at the output during Vendors of the FPGAs described herein provide Design a load transient indicating poor phase margin. Any tools that estimate core current requirements based on ringing in the output should be avoided as this may the internal blocks utilized. result in instability with external component variation Over time, the voltages used to Power the core have or when operating at temperature extremes. steadily dropped. Modern cores utilize 65 nm, 45 nm AUX Voltage Considerations or even 40 nm geometry silicon processes and may Many FPGAs require a third Power Supply commonly operate from voltages as low as These lower referred to as the auxiliary rail or AUX.

6 Since the AUX. voltages are valuable to reduce Power dissipation in rail may Power internal clocks, phase-lock loops, or FPGAs. The trade o , however, is that keeping within transceivers, the amount of output voltage ripple on the voltage tolerance requirements becomes more this rail should be minimized. In some cases, additional challenging for the Power Supply designer. ferrite beads and capacitors ltering may be needed to Output Capacitance and Transient Considerations meet the application or FPGA noise requirements. In A good Power Supply Design will keep the core applications where noise is extremely important, a low voltage within tolerance at all times.

7 Most of the noise, high PSRR LDO, like the LP3878, should be Power Supply transient concerns can be managed by considered instead of a switching converter. properly selecting the bypass and bulk capacitances for the Power Supply . In general, every core ball or pin Sequencing Requirements connection should be bypassed directly under FPGAs The sequencing requirements vary depending on with high-quality X5R or X7R ceramic capacitors. the particular FPGA being used and many newer The values recommended for each of these capacitors FPGAs specify that no sequencing is required. While range from 1 F to 10 F and will generally be this is technically true for the FPGA, it is not the speci ed by FPGA manufacturers.

8 These capacitors optimal way to Design a Power solution. National provide a charge when FPGAs need to rapidly draw Semiconductor o ers several devices to address large spikes of current during high speed operations. sequencing requirements. The LM3880 is designed to Likewise, the bulk capacitance should be selected to address sequential sequencing of multiple Supply rails. provide charge during large steps of current, which This device is available in a small SOT-23 package and tend to occur during Power -on, application-start, can sequence up to three Supply rails. Many options or a change in application state. Before increasing are available to control the up and down, three- ag the amount of output capacitance to solve transient outputs sequencing timing.

9 National also provides droop issues, changes to the Power Supply should be devices to support customized ag order and timing. made that do not involve an increase in PCB area or component count. 2. Power designer Figure 1 illustrates a typical application circuit for the Figure 3 illustrates a typical voltage tracking LM3880. con guration for these devices. Master Supply LM3880. V CORE. FLAG1. VIN VIN Tracking Supply FLAG2. EN FLAG3 EN V IO. Power Power Power R1. GND Supply 1 Supply 2 Supply 3. SS/TRK. EN EN EN. R2. Figure 1. Simpli ed Buck Converter Schematic Figure 3. Typical voltage tracking con guration Voltage tracking is another method of sequencing Power supplies applicable to FPGAs and many Startup / Power -on Requirements processors.

10 The most common and generally When sequential sequencing is used in systems with recommended method to Power up FPGAs and other multiple voltage rails, as is the case with many FPGA. processors is to have the CORE voltage track the I/O solutions, it is likely that an output of one of the Power voltage during startup as shown in Figure 2. supplies could be pre-biased through various parasitic conduction paths. In this situation, how the Power Supply handles this pre-biased state can have an impact VCORE. on long term system reliability, or even the ability of VIO the Power Supply or FPGAs to start successfully. To Voltage avoid the pitfalls associated with a pre-biased startup, the Power Supply should not pull the output low if VENABLE 1.


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